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PDF AD9898 Data sheet ( Hoja de datos )
| Número de pieza | AD9898 | |
| Descripción | CCD Signal Processor with Precision Timing Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Correlated Double Sampler (CDS)
6 dB to 40 dB Variable Gain Amplifier (VGA)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 1 ns Resolution
On-Chip: 2-Channel Horizontal and
1-Channel RG Drivers
2-Phase H-Clock Modes
4-Phase Vertical Transfer Clocks
Electronic and Mechanical Shutter Modes
On-Chip Sync Generator with External Sync Option
Space Saving 48-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
CCD Signal Processor with
Precision Timing™ Generator
AD9898
GENERAL DESCRIPTION
The AD9898 is a highly integrated CCD signal processor for
digital still camera and digital video camera applications. It
includes a complete analog front end with A/D conversion
combined with a full function programmable timing generator.
A Precision Timing core allows adjustment of high speed clocks
with 1 ns resolution at 20 MHz operation.
The AD9898 is specified at pixel rates as high as 20 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 10-bit A/D converter. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias pulse. Operation is
programmed using a 3-wire serial interface.
Packaged in a space saving 48-Lead LFCSP, the AD9898 is
specified over an operating temperature range of –20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9898
6dB TO 40dB
CDS
VGA
REFT REFB
VREF
ADC
10
DOUT
RG
H1, H2
V1, V2, V3, V4
VSG1, VSG2
HORIZONTAL
2 DRIVERS
4
V-H
CONTROL
2
CLAMP
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
DCLK1
FD/DCLK2
MSHUT
STROBE
VSUB SUBCK
HD VD SYNC CLI
SL SCK SDATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD9898
TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz, unless otherwise noted.)
Parameter
Symbol
Min Typ Max Unit
MASTER CLOCK, CLI
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLAMP PULSES*
CLPOB Pulsewidth
tCONV
tCLIDLY
50
20 25
6
4 10
ns
ns
ns
Pixels
AFE SAMPLE LOCATION* (See Figure 13)
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS (See Figure 15)
Output Delay from DCLK Rising Edge
Pipeline Delay from SHP/SHD Sampling
tS1 20 25
tOD 9
9
Pixels
ns
Cycles
SERIAL INTERFACE (See Figures 7 and 8)
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
*Parameter is programmable.
Specifications subject to change without notice.
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
REV. 0
–5–
5 Page 
AD9898
Table I. Control Register Address Map (Register Names Are Subject to Change)
Bit Default Register
Address Content Width Value Name
Register Description
0A 23
22
(21:16)
(15:12)
(VD (11:10)
SyncReg)* 9
8
(7:4)
(3:2)
1
0
1
1
6
4
2
1
1
4
2
1
1
0
0
0x00
0
0
0
0
C
3
0
0
FDPOL
VSGMASK
SYNCCNT
SVREP_MODE
HBLKEXT
HPULSECNT
SPATLOGIC
SVOS
SPAT_EN
MODE
Unused
FD Polarity Control (0 = Low, 1 = High)
VSG Masking (See Table XXIII)
External SYNC Setting
Super Vertical Repetition Mode
H Pulse Blanking Extend Control
H Pulse Control during Blanking
SPAT Logic Setting (See Table XX)
Second V Output Setting (10 = Output Repetition 1)
SPAT Control (0 = SPAT Disable, 1 = SPAT Enable)
Mode Control Bit (0 = Mode_A, 1 = Mode_B)
0B (23:22)
21
20
(VD (19:17)
SyncReg)* 16
2
1
1
3
1
15
(14:12)
11
(10:0)
1
3
1
11
0
1
1
0
0
0
0
0
0x7FF
SUBCK_EN
VSG_EN
STROBE_EN
SUBCKNUM_HP
SUBCKNUM
Unused
SUBCK Output Enable Control (0 = Disable, 1 = Enable)
VSG Output Enable Control (0 = Disable, 1 = Enable)
Unused
STROBE Output Control (0 = STROBE Output Held Low,
1 = STROBE Output Enabled)
Unused
High Precision Shutter SUBCLK Pulse Position/Number
Unused
Total Number of SUBCKs per Field
0C (23:21)
20
(19:18)
(VD 17
SyncReg)* 16
15
(14:12)
11
(10:0)
3
1
2
1
1
1
3
1
11
0
0
0
0
0
0
0
0
0x000
MSHUTINIT
MSHUTEN
MSHUTPOS_HP
MSHUTPOS
Unused
MSHUT Initialize (1 = Forces MSHUT Low)
Unused
Unused
MSHUT Control ( 0 = MSHUT Held at Last State, 1 = MSHUT Output)
Unused
MSHUT Position during High Precision Operation
Unused
MSHUT Position during Normal Operation
0D (23:17)
16
(VD (15:11)
SyncReg)* (10:0)
7
1
5
11
0
0x000
VSUBPOL
VSUBTOG
Unused
VSUB Active Polarity (0 = Low, 1 = High)
Unused
VSUB Toggle Position. Active starting line in any field.
0E (23:21)
20
(19:18)
(VD 17
SyncReg)* 16
(15:10)
(9:0)
3
1
2
1
1
6
10
0
0
0
0
0
0x00
0x000
VGAGAIN
Unused
Unused. Test Mode. Should be set = 0.
Unused
Unused. Test Mode. Should be set = 0.
Unused. Test Mode. Should be set = 0.
Unused
VGA Gain
D5
(23:4) 20
0x00000
3 1 1 DCLK2SEL
2 1 0 DCLK1SEL
(1:0)
2
0
CLKDIV
Unused
DCLK2 Selector (0 = Select Internal FD Signal to be Output on FD/
DCLK2 Pin 16, 1 = Select CLI to be Output on FD/DCLK2 Pin 16)
DCLK1 Selector (0 = Select DLL Version for DCLK1 Output,
1 = Select CLI for DCLK1 Output)
Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4)
D6
(23:1) 23
0x000000
0 1 1 SLAVE_MODE
Unused
Operating Mode ( 0 = Master Mode, 1 = Slave Mode)
*This register defaults to VD synchronous mode type at power up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the
register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Addr 0x01).
REV. 0
–11–
11 Page | ||
| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet AD9898.PDF ] | |
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