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PDF AD9816 Data sheet ( Hoja de datos )
| Número de pieza | AD9816 | |
| Descripción | Complete 12-Bit 6 MSPS CCD/CIS Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
12-Bit 6 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel or 1-Channel Operation
Correlated Double Sampling
8-Bit Programmable Gain
8-Bit Offset Adjustment
PGA Output Monitor
Input Clamp Circuitry
Internal Voltage Reference
3-Wire Serial Interface
+3.3 V/+5 V Digital Output Compatibility
44-Lead MQFP Package
Low Power CMOS: 420 mW Typ
Complete 12-Bit 6 MSPS
CCD/CIS Signal Processor
AD9816
PRODUCT DESCRIPTION
The AD9816 is a complete analog signal processor for CCD
and CIS applications. Included is all the necessary circuitry to
perform three-channel conditioning and sampling for a variety
of imaging applications.
The signal chain consists of an input clamp, correlated double
sampler (CDS), offset adjust DAC, programmable gain ampli-
fier and a 12-bit A/D converter. The CDS and input clamp may
be disabled for CIS applications.
The internal registers are programmed using a 3-wire serial
interface and provide adjustment of the gain, offset and operat-
ing mode.
The AD9816 operates from a +5 V supply, typically consumes
420 mW of power and is packaged in a 44-lead MQFP.
VINR
VING
VINB
OFFSET
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS CAPT CAPB CML PGAOUT VREF DVDD DVSS DRVDD DRVSS
؎100mV
CLAMP/CDS
+
DAC
1X–6X
PGA
AD9816
BANDGAP
REFERENCE
CLAMP/CDS
CLAMP/CDS
+
DAC
PGA
PGA
+
DAC
8
OFFSET
REGISTERS
MUX
MUX
REGISTER
CONFIGURATION
REGISTER
8
RR
GAIN
G G REGISTERS
BB
12-BIT 12
ADC
DIGITAL
CONTROL
PORT
OEB
DOUT
11:0
SCLK
SLOAD
SDATA
CDSCLK1 CDSCLK2 ADCCLK
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD9816
ANALOG
INPUTS
PIXEL n
tAD
PIXEL (n+1)
PIXEL (n+2)
CDSCLK2
ADCCLK
OUTPUT
DATA
ϽD11:D0Ͼ
PGAOUT_T
PGAOUT_C
tADC2
tC2
tADCLK
PIXEL (n–4)
PIXEL (n–1)
tCRB
tC2AD
tADCLK
PIXEL (n–3)
tOD
PIXEL (n–2)
PIXEL n
PIXEL (n+1)
Figure 4. 1-Channel SHA Mode Timing
PIXEL (n–1)
PIXEL (n+2)
PIXEL (n+m)
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OPTICAL BLACK OR DUMMY PIXELS
EFFECTIVE PIXELS
Figure 5. Line Clamp Timing for 3-Channel CDS Mode
ADCCLK
OUTPUT
DATA
ϽD11:D0Ͼ
OEB
tOD
tHZ
Figure 6. Output Enable Timing
tDV
REV. A
–5–
5 Page 
AD9816
CIRCUIT DESCRIPTIONS
Analog Input Configuration for CDS and SHA Mode
CDS Mode Operation
Figure 13 shows the equivalent input circuit for the CDS mode
of operation. The CCD signal is connected to the AD9816’s
analog inputs through a coupling capacitor CIN. The CCD
reference level is clamped during the CDSCLK1 pulse, when
the clamp switch closes and connects the externally-generated
3 V bias to the analog input. After the clamp switch opens
(CDSCLK1 low), the CCD data level will be level shifted by
the voltage held across CIN, and the SHA will sample the input
signal when the CDSCLK2 pulse goes low (see Figures 1 and 3
for CDS mode timing). In this sampling technique, the CDS
function is effectively performed across the input capacitor, CIN.
This CDS method has two additional considerations. First, the
CCD signal cannot be dc-coupled into the AD9816, because
the input capacitor is required. Second, the input clamp of the
AD9816 is operating as a pixel clamp, and must be asserted on
every pixel for true CDS operation. If line clamp operation is
desired, CDSCLK1 may be used at the start of each line to set
the proper dc voltage on CIN. Then, during the effective pixels
of each line, CDSCLK1 can be held low while CDSCLK2
samples the data levels of each pixel. Figure 5 shows the timing
for line clamp operation.
CCD SIGNAL
AD9816
RS CIN VING IBIAS
11
CSTRAY
+5V
1F 0.1F
1.0k⍀
16
OFFSET
1.5k⍀
3V
BUFFER
CLAMP
SWITCH
SHA
17 18
CDSCLK1 CDSCLK2
Figure 13. CDS Mode Input Circuit (All Channels Identical)
Input Signal Range for CDS Mode
An input dc bias level of 3 V allows a maximum 3 V p-p signal
swing from the CCD. Figure 14 shows a typical full-scale input
waveform to the AD9816, illustrating the allowable input range.
With a reference level of 3 V, the AD9816 can tolerate up to
2 V of reset feedthrough above the reference level. The inputs
of the AD9816 can also handle an input signal down to
AVSS – 0.3 V without any saturation recovery issues. Although
an input level below zero volts will be clipped to the ADC’s full-
scale output code, the input stage can respond quickly enough
to accurately process the next pixel that falls into the linear
input range. Any signals below AVSS – 0.3 V will turn on the
input protection diodes, and recovery from the saturated condi-
tion may take up to several milliseconds.
Input Capacitor CIN
The recommended value for CIN is 1200 pF. This value has
been selected to provide the best overall performance when
considering three factors: input attenuation, linearity and signal
droop. The value of CIN may be optimized for a particular ap-
plication if these three factors are understood.
1. Attenuation (Gain Error)
The input voltage will be attenuated by the interaction of
CIN and CSTRAY. CSTRAY is less than 10 pF, which results in
an attenuation of about 0.8% when CIN is 1200 pF. The gain
error will increase accordingly as the value of CIN is decreased.
2. Linearity
The input capacitance of the AD9816 is shown in Figure 8
as CSTRAY. A small portion of this capacitance is junction
capacitance, which will vary nonlinearly as the input voltage
to the AD9816 changes. When the input voltage is attenu-
ated by the combination of CIN and CSTRAY, there will be a
small nonlinear component caused by the input junction
capacitance. The magnitude of the junction capacitance will
cause a 1 LSB (0.024%) nonlinearity over the 3 V input
range when a 1200 pF CIN is used. This nonlinearity will
increase if a smaller CIN is used.
3. Droop
The input bias current of the AD9816 is typically 10 nA and
is constant regardless of the AD9816’s input voltage. The
droop of the voltage across CIN can be calculated with the
following equation:
dV = iBIAS × (t)
CIN
where t is the time between clamp intervals. Between the
adjacent pixels of a scanned line, this droop will be insignifi-
cant. Between scanned lines, a 1 ms delay will produce a
droop of about 10 mV, which can be easily clamped on the
first pixel of the next line. If the value of CIN is reduced, the
droop will increase accordingly.
5V MAX RESET FEEDTHROUGH
3V REFERENCE LEVEL
(SET BY INPUT CLAMP)
MAX PEAK-PEAK SIGNAL
0V MAX DATA LEVEL
–0.3V MAX SATURATED DATA LEVEL
Figure 14. CCD Input Signal Clamped to 3 V
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD9816.PDF ] | |
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