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PDF CS8420 Data sheet ( Hoja de datos )
| Número de pieza | CS8420 | |
| Descripción | DIGITAL AUDIO SAMPLE RATE CONVERTER | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS8420
Digital Audio Sample Rate Converter
Features
General Description
Complete IEC60958, AES3, S/PDIF, EIAJ
CP1201-compatible Transceiver with
Asynchronous Sample Rate Converter
Flexible 3-wire Serial Digital I/O Ports
8-kHz to 108-kHz Sample Rate Range
www.DataSheet4U.com
1:3 and 3:1 Maximum Input to Output Sample
Rate Ratio
128 dB Dynamic Range
-117 dB THD+N at 1 kHz
Excellent Performance at Almost a 1:1 Ratio
Excellent Clock Jitter Rejection
24-bit I/O Words
Pin and Microcontroller Read/Write Access to
Channel Status and User Data
Microcontroller and Stand-Alone Modes
The CS8420 is a stereo digital audio sample rate con-
verter (SRC) with AES3-type and serial digital audio
inputs, AES3-type and serial digital audio outputs, and
includes comprehensive control ability via a 4-wire mi-
crocontroller port. Channel status and user data can be
assembled in block-sized buffers, making
read/modify/write cycles easy.
Digital audio inputs and outputs may be 24, 20, or 16
bits. The input data can be completely asynchronous to
the output data, with the output data being synchronous
to an external system clock.
The CS8420 is available in a 28-pin SOIC package in
both Commercial (-10º to +70º C) and Automotive
grades (-40º to +85º C). The CDB8420 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions.
Please refer to “Ordering Information” on page 93 for or-
dering information.
Target applications include CD-R, DAT, MD, DVD and
VTR equipment, mixing consoles, digital audio trans-
mission equipment, high-quality D/A and A/D
converters, effects processors, and computer audio
systems.
VA+ AGND FILT RERR RMCK
VD+ DGND
ILRCK
ISCLK
SDIN
RXP
RXN
Serial
Audio
Input
Sample
Rate
Converter
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
Receiver
Clock & AES3
Data
S/PDIF
Recovery Decoder
C & U bit
Data
Buffer
AES3
S/PDIF
Encoder
Driver
TXP
TXN
Misc.
Control
Control
Port &
Registers
Output
Clock
Generator
H/S RST
EMPH U TCBL SDA/ SCL/ AD1/ AD0/ INT
CDOUT CCLK CDIN CS
OMCK
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
APRIL '07
DS245F4
1 page  
CS8420
Figure 35.Consumer Input Circuit ............................................................................................................. 80
Figure 36.TTL/CMOS Input Circuit ............................................................................................................ 80
Figure 37.Channel Status Data Buffer Structure ....................................................................................... 81
Figure 38.Channel Status Block Handling When Fso is Not Equal to Fsi ................................................. 82
Figure 39.Flowchart for Reading the E Buffer ........................................................................................... 82
Figure 40.Flowchart for Writing the E Buffer ............................................................................................. 83
Figure 41.PLL Block Diagram ................................................................................................................... 87
Figure 42.Recommended Layout Example ............................................................................................... 88
Figure 43.Jitter Tolerance Template ......................................................................................................... 90
Figure 44.Revision D Jitter Attenuation ..................................................................................................... 90
Figure 45.Revision D1 Jitter Attenuation ................................................................................................... 90
LIST OF TABLES
www.DataSheet4U.com Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN ...................... 28
Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK ........................... 28
Table 3. Non-SRC Delay ........................................................................................................................... 29
Table 4. Summary of all Bits in the Control Register Map ........................................................................ 33
Table 5. Hardware Mode Definitions ......................................................................................................... 55
Table 6. Serial Audio Output Formats Available in Hardware Mode ......................................................... 55
Table 7. Serial Audio Input Formats Available in Hardware Mode ............................................................ 55
Table 8. Hardware Mode 1 Start-Up Options ............................................................................................ 56
Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function ...................................................................... 60
Table 10. HW Mode 2 Serial Audio Port Format Selection ....................................................................... 60
Table 11. Hardware Mode 2 Start-Up Options .......................................................................................... 60
Table 12. Hardware Mode 3 Start-Up Options .......................................................................................... 64
Table 13. Hardware Mode 4 Start-Up Options .......................................................................................... 68
Table 14. Hardware Mode 5 Start-Up Options .......................................................................................... 71
Table 15. HW 6 COPY/C and ORIG Pin Function .................................................................................... 75
Table 16. HW 6 Serial Port Format Selection ........................................................................................... 75
Table 17. Second Line Part Marking ......................................................................................................... 88
Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz ................................................................................... 89
Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz* ................................................................................ 89
Table 20. Locking to the ILRCK Input ....................................................................................................... 89
DS245F4
5
5 Page 
CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
Parameter
Symbol Min Typ Max Units
SCL Clock Frequency
fscl - - 100 kHz
Bus Free Time Between Transmissions
tbuf 4.7 - - μs
Start Condition Hold Time (prior to first clock pulse)
thdst 4.0 - - μs
Clock Low Time
tlow 4.7 - - μs
Clock High Time
thigh 4.0 - - μs
Setup Time for Repeated Start Condition
tsust 4.7 - - μs
SDA Hold Time from SCL Falling
(Note 16) thdd 0 - - μs
www.DataSheetS4UD.AcomSetup Time to SCL Rising
tsud 250 - - ns
Rise Time of Both SDA and SCL Lines
tr - - 25 ns
Fall Time of Both SDA and SCL Lines
tf - - 25 ns
Setup Time for Stop Condition
tsusp 4.7 - - μs
16. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
Stop Start
Repeated
Start
SDA
SCL
t buf t hdst
t high
t hdst
tf
t low t hdd
t sud
t sust
tr
Figure 4. I²C Mode Timing
Stop
t susp
DS245F4
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