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PDF AD7731 Data sheet ( Hoja de datos )
| Número de pieza | AD7731 | |
| Descripción | Low Noise/ High Throughput 24-Bit Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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FEATURES
24-Bit Sigma-Delta ADC
16 Bits p-p Resolution at 800 Hz Output Rate
Programmable Output Rates up to 6.4 kHz
Programmable Gain Front End
؎0.0015% Nonlinearity
Buffered Differential Inputs
Programmable Filter Cutoffs
FASTStep™* Mode for Channel Sequencing
Single Supply Operation
APPLICATIONS
Process Control
PLCs/DCS
Industrial Instrumentation
Low Noise, High Throughput
24-Bit Sigma-Delta ADC
AD7731
GENERAL DESCRIPTION
The AD7731 is a complete analog front-end for process control
applications. The device has a proprietary programmable gain
front end that allows it to accept a range of input signal ranges,
including low level signals, directly from a transducer. The sigma-
delta architecture of the part consists of an analog modulator
and a low pass programmable digital filter, allowing adjustment
of filter cutoff, output rate and settling time.
The part features three buffered differential programmable gain
analog inputs (which can be configured as five pseudo-differential
inputs), as well as a differential reference input. The part oper-
ates from a single +5 V supply and accepts seven unipolar ana-
log input ranges: 0 to +20 mV, +40 mV, +80 mV, +160 mV,
+320 mV, +640 mV and +1.28 V, and seven bipolar ranges:
± 20 mV, ± 40 mV, ± 80 mV, ± 160 mV, ± 320 mV, ± 640 mV and
± 1.28 V. The peak-to-peak resolution achievable directly from
the part is 16 bits at an 800 Hz output rate. The part can switch
between channels with 1 ms settling time and maintain a perfor-
mance level of 13 bits of peak-to-peak resolution.
The serial interface on the part can be configured for three-wire
operation and is compatible with microcontrollers and digital
signal processors. The AD7731 contains self-calibration and
system calibration options and features an offset drift of less
than 5 nV/°C and a gain drift of less than 2 ppm/°C.
The part is available in a 24-lead plastic DIP, a 24-lead SOIC
and 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
NC
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AVDD
DVDD
REF IN(–) REF IN(+)
AVDD
100nA BUFFER
MUX
PGA
AD7731
SIGMA-DELTA A/D CONVERTER
SIGMA-
DELTA
MODULATOR
PROGRAMMABLE
DIGITAL
FILTER
100nA
AGND
SERIAL INTERFACE
AND CONTROL LOGIC
CLOCK
GENERATION
REGISTER BANK
CALIBRATION
MICROCONTROLLER
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
AGND
DGND
POL
RDY
RESET
*FASTStep is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
1 page  
AD7731
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3 V
AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Output Voltage (D0, D1) to DGND . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Model
AD7731BN
AD7731BR
AD7731BRU
EVAL-AD7731EB
ORDERING GUIDE
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Package Description
Plastic DIP
Small Outline
Thin Shrink Small Outline (TSSOP)
Package Options
N-24
R-24
RU-24
TO OUTPUT
PIN
50pF
ISINK (800µA AT DVDD = +5V
100µA AT DVDD = +3V)
+1.6V
ISOURCE (200µA AT DVDD = +5V
100µA AT DVDD = +3V)
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7731 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
5 Page 
AD7731
Output Noise (CHP = 1, SKIP = 0)
Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in
chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. The numbers are generated with a mas-
ter clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0 V. The out-
put update rate is selected via the SF0 to SF11 bits of the Filter Register. Table IV, meanwhile, shows the output peak-to-peak
resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in
Table IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on
rms noise but on peak-to-peak noise.
The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges. To calcu-
late the number for Table IV for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.
Table III. Output Noise vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
Typical Output RMS Noise in nV
Output –3 dB
SF
Data Rate Frequency Word
50 Hz
100 Hz
150 Hz
200 Hz
400 Hz
800 Hz
1.97 Hz
3.95 Hz
5.92 Hz
7.9 Hz
15.8 Hz
31.6 Hz
2048
1024
683
512
256
128
Settling Time
Input Range
Normal Fast Step ؎1.28 V ؎640 mV ؎320 mV ؎160 mV ؎80 mV ؎40 mV ؎20 mV
440 ms
220 ms
147 ms
110 ms
55 ms
27.5 ms
40 ms
20 ms
13.3 ms
10 ms
5 ms
2.5 ms
700
980
1230
1260
2000
3800
425
550
700
840
1230
2100
265
330
445
500
690
1400
170
230
270
340
430
760
120 85
55
190 115 90
210 140 100
245 170 105
335 215 160
590 345 220
Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
Peak-to-Peak Resolution in Bits
Output –3 dB
SF
Data Rate Frequency Word
50 Hz
100 Hz
150 Hz
200 Hz
400 Hz
800 Hz
1.97 Hz
3.95 Hz
5.92 Hz
7.9 Hz
15.8 Hz
31.6 Hz
2048
1024
683
512
256
128
Settling Time
Input Range
Normal Fast Step ؎1.28 V ؎640 mV ؎320 mV ؎160 mV ؎80 mV ؎40 mV ؎20 mV
440 ms
230 ms
147 ms
110 ms
55 ms
27.5 ms
40 ms
30 ms
13.3 ms
10 ms
5 ms
2.5 ms
19
19
18.5
18.5
17.5
17
19
18.5
18
18
17.5
16.5
18.5 18.5
18.5 18
18 17.5
17.5 17.5
17 17
16 16
18 17.5 17
17 17 16
17 16.5 16
17 16.5 16
16.5 16
15.5
15.5 15
15
ON-CHIP REGISTERS
The AD7731 contains 12 on-chip registers that can be accessed
via the serial port of the part. These registers are summarized in
Figure 4 and in Table V, and described in detail in the following
sections.
COMMUNICATIONS REGISTER
DIN DIN
RS2 RS1 RS0
DOUT
DOUT
STATUS REGISTER
DOUT
DOUT
DIN
DATA REGISTER
MODE REGISTER
DOUT
DIN
FILTER REGISTER
DIN
DOUT
OFFSET REGISTER (x3)
DOUT
DIN
GAIN REGISTER (x3)
DOUT
DIN
TEST REGISTER
REGISTER
SELECT
DECODER
REV. 0
–11–
Figure 4. Register Overview
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7731.PDF ] | |
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