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PDF ADUC702 Data sheet ( Hoja de datos )
| Número de pieza | ADUC702 | |
| Descripción | Precision Analog Microcontroller 12-bit Analog I/O/ ARM7TDMI MCU | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
Precision Analog Microcontroller
12-bit Analog I/O, ARM7TDMI® MCU
ADuC702x Series
FEATURES
Analog I/O
Multi-Channel, 12-bit, 1MSPS ADC
- Up to 16 ADC channels *
Fully differential and single-ended modes
0 to VREF Analog Input Range
12-bit Voltage Output DACs
- Up to 4 DAC outputs available*
On-Chip 20ppm/°C Voltage Reference
On-Chip Temperature Sensor (±3°C)
Uncommitted Voltage Comparator
Microcontroller
ARM7TDMI Core, 16/32-bit RISC architecture
JTAG Port supports code download and debug
Clocking options: - Trimmed On-Chip Oscillator (± 3%)
- External Watch crystal
- External clock source
45MHz PLL with Programmable Divider
Memory
62k Bytes Flash/EE Memory, 8k Bytes SRAM
In-Circuit Download, JTAG based Debug
Software triggered in-circuit re-programmability
On-Chip Peripherals
UART, 2 X I2C and SPI Serial I/O
Up to 40-Pin GPIO Port*
4 X General Purpose Timers
Wake-up and Watchdog Timers
Power Supply Monitor
Three-phase 16-bit PWM generator*
PLA – Programmable Logic (Array)
Power
Specified for 3V operation
Active Mode: 3mA (@1MHz)
50mA (@45MHz)
Packages and Temperature Range
From 40 lead 6x6mm LFCSP to 80 pin LQFP*
Fully specified for –40°C to 125°C operation
Tools
Low-Cost QuickStart Development System
Full Third-Party Support
* Package, PWM, GPIO availability and number of Analog I/O
depend on part model. See page 9.
APPLICATIONS
Industrial Control and Automation Systems
Smart Sensors, Precision Instrumentation
Base Station Systems, Optical Networking
(See general description on page 11)
FUNCTIONAL BLOCK DIAGRAM
ADC0
ADC11
CMP0
CMP1
CMPOUT
VREF
XCLKI
XCLKO
RST
MUX
+
-
1MSPS
12-BIT ADC
TEMP
SENSOR
BANDGAP
REF
ADuC7026*
12-BIT DAC
12-BIT DAC
12-BIT DAC
12-BIT DAC
OSC
& PLL
PSM
POR
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
PLA
2kX32 SRAM
31kX16 FLASH/EEPROM
GPIO
4 GEN. PUR-
POSE TIMERS
SERIAL I/O
UART, SPI, I2C
JTAG
Three-
phase
PWM
EXT. MEMORY
INTERFACE
DAC0
DAC1
DAC2
DAC3
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
Figure 1
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
Parameter
POWER REQUIREMENTS 13, 14
Power Supply Voltage Range
AVDD – AGND and IOVDD - IOGND
Power Supply Current Normal Mode
Power Supply Current Idle Mode
Power Supply Current Power Down
Mode
ADuC702x
2.7
3.6
3mA
5
50
60
1
30
100
Unit
V min
V max
mA typ
mA max
mA typ
mA max
mA max
µA typ
µA max
ADuC702x Series
Test Conditions/Comments
1MHz clock
1MHz clock
45MHz clock
45MHz clock
External Crystal or Internal Osc ON
External Crystal or Internal Osc ON
1 Temperature Range -40° to +85°C
2 All ADC Channel Specifications are guaranteed during normal MicroConverter core operation.
3 These specification apply to all ADC input channels.
4 These numbers are not production tested but are supported by design and/or characterization data on production release.
5 Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint and achieve these specifications..
6 SNR calculation includes distortion and noise components.
7 Channel-to-channel crosstalk is measured on adjacent channels.
8 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
9 When using an external reference input pin, the internal reference must be disabled by setting the lsb in the REFCON Memeory Mapped Register to 0.
10 Endurance is qualified to 50,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, +25°C and +85°C. Typical endurance at 25°C is 70,000 cycles.
11 Retention lifetime equivalent at junction temperature (Tj) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime will derate with junction temperature.
12 Test carried out with a maximum of 20 I/O set to a low output level.
13 Power supply current consumption is measured in normal, idle and power-down modes under the following conditions:
Normal Mode: TBD
Idle Mode:
TBD
Power-Down: TBD
14 DVDD power supply current increases typically by TBD mA during a Flash/EE memory program or erase cycle.
Rev. PrB | Page 5 of 80
5 Page 
Preliminary Technical Data
ADuC702x Series
Pin# ADuC702X
7020 7021
7022
24 24
25 25
23
24
26 26
25
27 27
26
28 28
27
29 29
28
30 30
29
31 31
30
32 32
31
33 33
32
34 -
-
35 34
36 35
37 36
33
34
35
* I = Input, O = Output, S = Supply.
- No pin assigned.
Mnemonic
Type* Function
internal clock generator circuits
XCLKO
O Output from the crystal oscillator inverter
XCLKI
I
Input to the crystal oscillator inverter and input to the internal clock
generator circuits
P1.7/SPM7/PLAO[
0]
Serial Port Multiplexed:
I/O General Purpose Input-Output Port 1.7 / UART / SPI / Programmable
Logic Array Output Element 0
Serial Port Multiplexed:
P1.6/SPM6/PLAI[6] I/O General Purpose Input-Output Port 1.6 / UART / SPI / Programmable
Logic Array Input Element 6
Serial Port Multiplexed:
P1.5/SPM5/PLAI[5]
/IRQ3
I/O
General Purpose Input-Output Port 1.5 / UART / SPI / Programmable
Logic Array Input Element 5/ External Interrupt Request 3, active high
Serial Port Multiplexed:
P1.4/SPM4/PLAI[4]
/IRQ2
I/O
General Purpose Input-Output Port 1.4 / UART / SPI / Programmable
Logic Array Input Element 4/ External Interrupt Request 2, active high
Serial Port Multiplexed:
P1.3/SPM3/PLAI[3] I/O General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable
Logic Array Input Element 3
Serial Port Multiplexed:
P1.2/SPM2/PLAI[2] I/O General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable
Logic Array Input Element 2
Serial Port Multiplexed:
P1.1/SPM1/PLAI[1] I/O General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable
Logic Array Input Element 1
Serial Port Multiplexed:
P1.0/T1/SPM0/PLA
I[0]
I/O
General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 /
Programmable Logic Array Input Element 0
P4.2/PLAO[10]
I/O
General Purpose Input-Output Port 4.2 / Programmable Logic Array
Output Element 10
VREF
I/O
2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor
when using the internal reference.
AGND
S Analog Ground. Ground reference point for the analog circuitry
AVDD
S 3.3V Analog Power
Rev. PrB | Page 11 of 80
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADUC702.PDF ] | |
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