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PDF ADS7817C Data sheet ( Hoja de datos )

Número de pieza ADS7817C
Descripción 12-Bit Differential Input Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER
Fabricantes Burr-Brown Corporation 
Logotipo Burr-Brown Corporation Logotipo



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No Preview Available ! ADS7817C Hoja de datos, Descripción, Manual

®
ADS7817
OAPDSA7681578
ADS7817
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit Differential Input Micro Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q BIPOLAR INPUT RANGE
q TRUE DIFFERENTIAL INPUT
q 200kHz SAMPLING RATE
q MICRO POWER: 2.3mW at 200kHz
q POWER DOWN: 3µA Max
q AVAILABLE IN MSOP-8 PACKAGE
q SERIAL INTERFACE
q AC COMMON-MODE REJECTION
APPLICATIONS
q TRANSDUCER INTERFACE
q BATTERY OPERATED SYSTEMS
q REMOTE DATA ACQUISITION
q ISOLATED DATA ACQUISITION
q AC MOTOR CONTROL
DESCRIPTION
The ADS7817 is a 12-bit, 200kHz sampling analog-
to-digital converter (A/D) that features a high imped-
ance fully differential analog input. The reference
voltage can be varied from 100mV to 2.5V, with a
corresponding input-referred resolution between 49µV
and 1.22mV.
The differential input, low power, automatic power
down, and small size make the ADS7817 ideal for
direct connection to transducers in battery operated
systems, remote data acquisition, or multi-channel
applications. The ADS7817 is available in a plastic
mini-DIP-8, an SOIC-8, or an MSOP-8 package.
VREF
+In
–In
S/H Amp
SAR
CDAC
Comparator
Control
Serial
Interface
DOUT
DCLOCK
CS/SHDN
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-1369B
Printed in U.S.A., May, 2000

1 page




ADS7817C pdf
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1
10 100 1000
Ripple Frequency (kHz)
10000
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.9kHz, –0.5dB)
25 50
Frequency (kHz)
75
100
73
72
71
70
69
68
67
1
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SNR
SINAD
10
Input Frequency (kHz)
100
95
90
85
80
75
70
65
1
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
SFDR
THD
10
Input Frequency (kHz)
–95
–90
–85
–80
–75
–70
–65
100
80
70
60
50
40
30
20
10
–60
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT LEVEL
–50 –40 –30 –20 –10
Input Level (dB)
0
CHANGE IN INTEGRAL LINEARITY and DIFFERENTIAL
LINEARITY vs SAMPLE RATE
1.5
1.0 Change in Integral
Linearity (LSB)
0.5
0
–0.5
0
Change in Differential
Linearity (LSB)
80 160 240 320
Sample Rate (kHz)
400
®
5 ADS7817

5 Page





ADS7817C arduino
1.4V
DOUT
3k
100pF
CLOAD
Test Point
Load Circuit for tdDO, tr, and tf
DOUT
tr
VOH
VOL
tf
Voltage Waveforms for DOUT Rise and Fall Times tr, and tf
DCLOCK
DOUT
thDO
VIL
tdDO
VOH
VOL
Voltage Waveforms for DOUT Delay Times, tdDO
Test Point
DOUT
3k
100pF
CLOAD
VCC
tdis Waveform 2, ten
tdis Waveform 1
Load Circuit for tdis and tden
CS/SHDN
VIH CS/SHDN
DOUT
Waveform 1(1)
DOUT
Waveform 2(2)
90%
tdis
10%
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
DCLOCK
DOUT
FIGURE 5. Timing Diagrams and Test Circuits for the Parameters in Table I.
1000
1000
12
VOL
ten
B11
Voltage Waveforms for ten
100 100
10
1
1
TA = 25°C
VCC = +5V
VREF = +2.5V
fCLK = 3.2MHz
10 100
Sample Rate (kHz)
1000
10
1
1
TA = 25°C
VCC = +5V
VREF = +2.5V
fCLK = 16 • fSAMPLE
10 100
Sample Rate (kHz)
1000
FIGURE 6. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Directly with
Sample Rate.
FIGURE 7. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
®
11 ADS7817

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