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PDF AK5351 Data sheet ( Hoja de datos )

Número de pieza AK5351
Descripción Enhanced Dual bit 20bit ADC
Fabricantes Asahi Kasei Microsystems 
Logotipo Asahi Kasei Microsystems Logotipo



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No Preview Available ! AK5351 Hoja de datos, Descripción, Manual

ASAHI KASEI
[AK5351]
AK5351
Enhanced Dual bit ∆Σ 20bit ADC
GENERAL DESCRIPTION
The AK5351 is a 20-bit, 64x oversampling rate(64fs), 2-channel A/D converter for stereo digital systems.
The ∆Σ modulator in the AK5351 uses the new developed Enhanced Dual bit architecture. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as the conventional Single bit way. The AK5351 is suitable for digital surround and Hi-Fi
audio application such as Car-audio, MD, etc. Analog inputs of the AK5351 are normally Full-differential inputs,
while they are also acceptable Single-ended inputs.
The AK5351 is available in a small 24pin VSOP package which will reduce your system space.
FEATURES
† Full-differential / Single-ended inputs
† S/(N+D): 97dB
† DR, S/N: 103dB
† Linear phase digital filter
Pass band: 0~22kHz(@fs=48kHz)
Pass band ripple: ±0.005dB
Stop band attenuation: 80dB
† Digital HPF for DC-offset cancel
† Master clock: 256fs/384fs
† Power supply: 5V±10%
† Small package: 24pinVSOP
0166-E-00
-1-
1997/4

1 page




AK5351 pdf
ASAHI KASEI
[AK5351]
ABSOLUTE MAXIMUM RATINGS
(AGND,DGND=0V; Note 1 )
Parameter
Symbol
min
max
DC Power Supply:Analog Power(VA pin)
VA -0.3
6.0
Digital Power(VD pin) (Note 2 )
VD -0.3 6.0/VB+0.3
Substrate Power(VB pin)
VB -0.3
6.0
Input Current (Any pin except supplies)
IIN -
±10
Analog Input Voltage
VINA -0.3 6.0/VA+0.3
AINL+,AINL-,AINR+,AINR-pins (Note 2 )
Digital Input Voltage
(Note 2 )
VIND
-0.3 6.0/VB+0.3
Ambient Temperature
Ta -40
85
Storage Temperature
Tstg -65
150
Note 1 : All voltage with respect to ground.
Note 2 : Absolute maximum value is the highest voltage in 6.0V, VA+0.3V and VB+0.3V.
Units
V
V
mA
V
V
°C
°C
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,DGND=0V; Note 1 )
Parameter
DC Power Supplies: Analog Power
Digital Power(VD pin)
(VB pin) (Note 3 )
Symbol
VA
VD
VB
min
4.50
4.50
4.50
typ
5.0
5.0
5.0
max
5.50
VB
5.50
Units
V
V
V
Note 1 : All voltages with respect to ground.
Note 3 : The VA and VB are connected together through the chip substrate and have several ohms
resistance. The VA and VB should be powered at the same time or earlier than VD.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
0166-E-00
-5-
1997/4

5 Page





AK5351 arduino
ASAHI KASEI
„ Serial Data Interface
[AK5351]
Audio Serial Interface has four kinds of mode, it can be changed by SMODE1 and SMODE2 pins. Data format
is MSB first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
1) SLAVE mode
SMODE1
L
H
L
H
SMODE2
Mode
L Slave Mode: 20bit, MSB justified
L Master Mode: Similar to I2S
H Slave Mode: I2S
H Master Mode: I2S
Table 2 . Serial Interface
L/R polarity
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
An output channel is defined by LRCK. Both channel data are output in sequence, in order of the Lch first then
Rch at the rate of fs. Data bits are clocked out via the SDATA pin at SCLK rate. Figure 1 and Figure 3 shows
data output timing at SCLK=64fs. FSYNC enables SCLK to start clocking out data. The MSB is clocked out by
the LRCK edge. SCLK causes the ADC to output succeeding bits when FSYNC is high. However, as I 2S slave
mode ignores FSYNC, it should hold "L" or "H".
2) MASTER mode
In MASTER mode, the A/D converter is driven from a master clock(MCLK:256fs/384fs) and outputs all other
clocks(LRCK, SCLK). The falling edge of SCLK causes the ADC to output each bit. Figure 2 and Figure 4
shows the output timing. 2x fs clock of 50% duty is output via the FSYNC pin. FSYNC rises one SCLK cycle
after the transition of LRCK edges and stays high during 16 serial clocks(16*tSLK). Upper 16 bit data is output
during FSYNC "H", lower 4 bit is output after FSYNC "L" transition.
0166-E-00
Figure 1 . Data Output Timing (Slave mode)
- 11 -
1997/4

11 Page







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