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PDF AK4124 Data sheet ( Hoja de datos )
| Número de pieza | AK4124 | |
| Descripción | 192kHz / 24Bit High Performance Asynchronous SRC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4124]
AK4124
192kHz / 24Bit High Performance Asynchronous SRC
GENERAL DESCRIPTION
AK4124 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to
216kHz. The output sample rate is from 8kHz to 216kHz. By using the AK4124, the system can take very
simple configuration because the AK4124 has an internal PLL and does not need any master clock at
slave mode. Then the AK4124 is suitable for the application interfacing to different sample rates like
high-end Car Audio, DVD recorder, etc.
FEATURES
1. SRC
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (fsi) : 8kHz ∼ 216kHz
• Output Sample Rate (fso) : 8kHz ∼ 216kHz
• Input to Output Sample Rate Ratio : 1/6 to 6
• THD+N : −130dB
• Dynamic Range : 140dB (A-weighted)
• I/F format : MSB justified, LSB justified and I2S compatible
• PLL for Internal Operation Clock
• Clock for Master mode : 128/192/256/384/512/768fsi, 128/192/256/384/512/768fso
• SRC Bypass mode
• Soft Mute Function
2. Power Supply
• AVDD, DVDD: 3.0 ∼ 3.6V (typ. 3.3V)
3. Ta = −40 ∼ 85°C
4. Package : 30pin VSOP
IDIF2 IDIF1 IDIF0 AVDD AVSS DVDD DVSS ODIF1 ODIF0
IBICK
ILRCK
SDTI
PLL2
PLL1
PLL0
Serial
Audio
I/F
PLL
SRC
Serial
Audio
I/F
OBIT1
OBIT0
OLRCK
OBICK
SDTO
OMCLK
PDN
SMUTE
DITHER
UNLOCK IMCLK
CMODE2 CMODE1 CMODE0
MS0288-E-01
-1-
2004/08
1 page  
ASAHI KASEI
[AK4124]
Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
FILT
SMUTE, DITHER
IMCLK, OMCLK
UNLOCK
Setting
This pin should be open.
These pins should be connected to DVSS.
These pins should be connected to DVSS in slave mode.
This pin should be open.
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter
Symbol
min
Power Supplies: Analog
AVDD
−0.3
Digital
DVDD
−0.3
|AVSS − DVSS| (Note 2) ∆GND
-
Input Current, Any Pin Except Supplies
IIN -
Digital Input Voltage
VIND
−0.3
Ambient Temperature (Power applied)
Ta −40
Storage Temperature
Tstg −65
Note 1. All voltages with respect to ground.
Note 2. AVSS, BVSS and DVSS must be connected to the same ground.
max
4.6
4.6
0.3
±10
DVDD+0.3
85
150
Units
V
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter
Symbol min typ
Power Supplies
Analog
AVDD 3.0 3.3
(Note 3)
Digital
DVDD 3.0 3.3
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD and DVDD is not critical.
max
3.6
AVDD
Units
V
V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0288-E-01
-5-
2004/08
5 Page 
ASAHI KASEI
[AK4124]
OPERATION OVERVIEW
System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK
(Mode 0 ∼ 2 of Table 2) or IBICK (Mode 4 ∼ 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And
an internal system clock is created by IMCLK (Mode 8 ∼ 15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when PDN pin = “L”.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when PDN pin = “L”. When in
BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode
0
1
2
3
4
5
6
7
IDIF2
L
L
L
L
H
H
H
H
IDIF1
L
L
H
H
L
L
H
H
IDIF0
SDTI Format
ILRCK IBICK IBICK Freq
L 16bit, LSB justified
≥ 32fsi
H 20bit, LSB justified
≥ 40fsi
L 24/20bit, MSB justified Input Input
≥ 48fsi
H 24/16bit, I2S Compatible
≥ 48fsi or 32fsi
L 24bit, LSB justified
≥ 48fsi
H
L
24bit, MSB justified
24bit, I2S Compatible
Output Output
64fs
64fs
H Reserved
Table 1. Input Audio Interface Format (Input PORT)
Master / Slave
Slave
Master
Mode Master / Slave
0
1
2 Slave
IMCLK = DVSS
3 IBICK = Input
4 ILRCK = Input
5
6
7
8
9
10 Master
11 IMCLK = Input
12 IBICK = Output
13 ILRCK = Output
14
15
PLL2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK
L
L
H
L
H
L
8k ∼ 96kHz
8k ∼ 216kHz
16k ∼ 216kHz
(Note 1)
Depending on
IDIF2-0
Not
needed.
(Note 4)
HH
Reserved
L
L
H
H
L
H
L
H
8k ∼ 216kHz
(Note 2)
32fsi (Note 3)
64fsi
128fsi
64fsi
Not
needed.
(Note 4)
L L 8k ∼ 216kHz
128fs
L H 8k ∼ 108kHz
256fs
H L 8k ∼ 54kHz
512fs
H H 8k ∼ 216kHz 64fs
L L 8k ∼ 216kHz
128fs
192fs
L H 8k ∼ 108kHz
384fs
H L 8k ∼ 54kHz
768fs
H H 8k ∼ 216kHz
192fs
Table 2. PLL Setting (Input PORT)
SMUTE
(Note 5)
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 2. The IBCIK must be continuous except when the clocks are changed.
Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
Note 4. Fixed to DVSS.
Note 5. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
MS0288-E-01
- 11 -
2004/08
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AK4124.PDF ] | |
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