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PDF AT91M55800 Data sheet ( Hoja de datos )
| Número de pieza | AT91M55800 | |
| Descripción | ARM Thumb Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Utilizes the ARM7TDMI™ ARM Thumb Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-Circuit Emulation)
• 8K Bytes Internal RAM
• Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 128M Bytes
– 8 Chip Selects
– Software Programmable 8/16-bit External Databus
www.Da•ta8S-hleeevte4lUP.croiomrity, Individually Maskable, Vectored Interrupt Controller
– 8 External Interrupts, Including a High-priority, Low-latency Interrupt Request
• 58 Programmable I/O Lines
• 6-channel 16-bit Timer/Counter
– 6 External Clock Inputs and 2 Multi-purpose I/O Pins per Channel
• 3 USARTs
• Master/Slave SPI Interface
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• 8-channel 10-bit ADC
• 2-channel 10-bit DAC
• Clock Generator with On-chip Main Oscillator and PLL for Multiplication
– 3 to 20 MHz Frequency Range Main Oscillator
• Real-time Clock with On-chip 32 kHz Oscillator
– Battery Backup Operation and External Alarm
• 10-channel Peripheral Data Controller for USARTs, SPIs and DACs
• Advanced Power Management Controller (APMC)
– Normal, Wait, Slow, Standby and Power-down modes
• IEEE 1149.1 JTAG Boundary-scan on all Digital Pins
• Fully Static Operation: 0 Hz to 33 MHz
• 1.8V to 3.6V Core Operating Range
• 2.7V to 5.5V I/O Operating Range
• 2.4V to 3.6V Analog Operating Range
• 1.8V to 3.6V Backup Battery Operating Range
• 2.4V to 3.6V Oscillator and PLL Operating Range
• -40°C to +85°C Temperature Range
• Available in a 176-lead TQFP or 176-ball BGA Package
Description
The AT91M55800 is a member of the Atmel AT91 16/32-bit microcontroller family,
which is based on the ARM7TDMI processor core. This processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption. In addition, a large number of internally banked registers result in
very fast exception handling, making the device ideal for real-time control
applications.
The fully programmable External Bus Interface provides a direct connection to off-chip
memory in as fast as one clock cycle for a read or write operation. An eight-level prior-
ity vectored interrupt controller in conjunction with the Peripheral Data Controller
significantly improve the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By com-
bining the ARM7TDMI processor core with an on-chip RAM and a wide range of
peripheral functions on a monolithic chip, the Atmel AT91M55800 is a powerful micro-
controller that provides a highly-flexible and cost-effective solution to many ultra low-
power applications.
AT91
ARM® Thumb®
Microcontrollers
AT91M55800
Rev. 1288A–06/00
1
1 page  
Figure 1. 176-lead TQFP Pinout
132
133
AT91M55800
89
88
www.DataSheet4U.com
176
1
45
44
Figure 2. 176-ball BGA Pinout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
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5 Page 
AT91M55800
Product Overview
Power Supplies
The AT91M55800 has 5 kinds of power supply pins:
• VDDCORE pins, which power the chip core
• VDDIO pins, which power the I/O Lines
• VDDPLL pins, which power the oscillator and PLL cells
• VDDA pins, which power the analog peripherals ADC
and DAC
www.Da•taSVhDeeDt4BUU.copmins, which power the RTC, the 32768 Hz
oscillator and the Shut-down Logic of the APMC
VDDIO and VDDCORE are separated to reduce the core
power by supplying it with a lower voltage than the I/O
lines.
The following ground pins are provided:
• GND for both VDDCORE and VDDIO
• GNDPLL for VDDPLL
Table 1. Nominal Power
• GNDA for VDDA
• GNDBU for VDDBU
All these ground pins must be connected to the same volt-
age (generally the board electric ground) with wires as
short as possible. GNDPLL, GNDA and GNDBU are pro-
vided separately in order to allow the user to add a
decoupling capacitor directly between the power and
ground pads. When connecting the PLL filter resistor and
capacitor and decoupling capacitors of the main oscillator
crystal as short as possible to GNDPLL and decoupling
capacitors of the 32768 Hz crystal as short as possible to
GNDBU.
The main constraints applying to the different voltages of
the device are:
• VDDBU must be lower than or equal to VDDCORE
• VDDA must be higher than or equal to VDDCORE
• VDDCORE must be lower than or equal to VDDIO
The nominal power combinations supported by the
AT91M55800 are described in the following table:
VDDIO
VDDCORE
VDDA
VDDPLL
VDDBU
Maximum Operating Frequency
3V 3V 3V 3V 3V
33 MHz
3.3V
3.3V
3.3V
3.3V
3.3V
33 MHz
3V 2V 3V 3V 2V
16 MHz
5V
3.3V
3.3V
3.3V
3.3V
33 MHz
Input/Output Considerations
After the reset, the peripheral I/Os are initialized as inputs
to provide the user with maximum flexibility. It is recom-
mended that in any application phase, the inputs to the
AT91M55800 microcontroller be held at valid logic levels to
minimize the power consumption.
Master Clock
Clock source is provided in one of the following ways,
depending on programming in the APMC registers:
• From the 32768 Hz low-power oscillator that clocks the
RTC
• From the on-chip main oscillator together with a PLL
generates a software-programmable main clock in the
500 Hz to 33 MHz range. The main oscillator can be
bypassed to allow the user to enter an external clock
signal.
The Master Clock (MCK) is also provided as an output of
the device on the pin MCKO, whose state is controlled by
the APMC module.
Reset
Reset restores the default states of the user interface regis-
ters (defined in the user interface of each peripheral), and
forces the ARM7TDMI to perform the next instruction fetch
from address zero. Except for the program counter the
ARM7TDMI registers do not have defined reset states.
NRST Pin
NRST is active low-level input. It is asserted asynchro-
nously, but exit from reset is synchronized internally to the
MCK. At reset, the source of MCK is the Slow Clock (32768
Hz crystal), and the signal presented on MCK must be
active within the specification for a minimum of 10 clock
cycles up to the rising edge of NRST, to ensure correct
operation.
Watchdog Reset
The watchdog can be programmed to generate an internal
reset. In this case, the reset has the same effect as the
NRST pin assertion, but the pins BMS and NTRI are not
sampled. Boot Mode and Tri-state Mode are not updated. If
the NRST pin is asserted and the watchdog triggers the
internal reset, the NRST pin has priority.
11
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