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PDF AT75C310 Data sheet ( Hoja de datos )

Número de pieza AT75C310
Descripción Smart Internet Appliance Processor (SIAP)
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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No Preview Available ! AT75C310 Hoja de datos, Descripción, Manual

Features
ARM7TDMIARM® Thumb® Processor Core
Two 16-bit Fixed-point OakDSPCore® Cores
256 x 32-bit Boot ROM
88K Bytes of Integrated Fast RAM for Each DSP
Flexible External Bus Interface with Programmable Chip Selects
Dual Codec Interface
Multi-level Priority, Individually Maskable, Vectored Interrupt Controller
Three 16-bit Timer/Counters
Additional Watchdog Timer
Two USARTs with FIFO and Modem Control Lines
Industry Standard Serial Peripheral Interface (SPI)
Up to 23 General-purpose I/O Pins
On-chip DRAM Controller
JTAG Debug Interface
Software Development Suites Available for ARM7TDMI and OakDSPCore
Supported by a Wide Range of Ready-to-use Application Software, including
Multitasking Operating System, Networking, Modems, and Voice-processing Functions
Available in 160-lead PQFP Package
3.3V Power Supply
Description
The Atmel AT75C310 Smart Internet Appliance Processor (SIAP) is a high-perfor-
mance processor specially designed for Internet appliance applications, such as
Internet telephony (Voice over Internet Protocol VoIP). The AT75C310 is built
around an ARM7TDMI microcontroller core running at 20 MIPS with two DSP co-pro-
cessors running at 40 MIPS each all three processors delivering unmatched
performance for low power consumption.
In a typical standalone VoIP phone, one DSP handles the voice-processing functions
(voice compression, acoustic echo cancellation, etc.), while the other one deals with
the telephony functions (dialing, line echo cancellation, callerID detection, high-speed
modem, etc.). In such an application, the power of the ARM7TDMI allows it to run the
VoIP protocol stack as well as all the system control tasks.
Atmel provides the AT75C310 with three levels of software modules:
a special port of the Linux kernel as the proposed operating system
a comprehensive set of tunable DSP algorithms for modems and voice processing,
specially tailored to be run by the DSP subsystems
a broad range of application-level software modules such as H323 telephony or
POP-3/SMTP e-mail services
Smart Internet
Appliance
Processor
Electrical and
Mechanical
Characteristics
AT75C310
Rev. 1370A07/00
1

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AT75C310 pdf
AT75C310
Figure 4. DRAM Write Cycle (Single Write)
NRASx
NCASx
tRC
tRAS
tRCD
tCSH
tRSH
tCAS
tASR
tRAH
tASC
tCAH
A
tRP
tCRP
NDWE
D
tWCS
tWCH
tDS tDH
Table 3. DRAM Write Cycle (Single Write) Timings
Symbol
Parameter
tRC
tRAS
tRP
tCSH
tCRP
tRCD
tRSH
tCAS
tASR
tRAH
tASC
tCAH
tWCS
tWCH
tDS
tDH
Read or Write Cycle Time
RAS Pulse Width
RAS Precharge Time
CAS Hold Time
CAS to RAS Precharge Time
RAS to CAS Delay Time
RAS Hold Time
CAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Write Command Setup Time
Write Command Hold Time
Data Setup Time
Data Hold Time
Min (ns)
125.0
82.0
42.0
61.0
49.0
41.0
29.0
20.0
1.5
22.0
15.0
21.0
18.0
21.0
8.0
21.0
Max (ns)
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AT75C310 arduino
Figure 10. Static Memory Read Cycle (LCD Mode, Two Wait States)
NCE3
tCSLCSH
tAVCSL
A
NSOE
(Standard Read Mode)
tRLRH
AT75C310
tCSHAH
NSOE
(Early Read Mode)
D
tRLDV1
tCSLDV
tAVDV
tRLDV2
tRHDH
tCSHDH
tRHAH
Table 9. Static Memory Read Cycle (LCD Mode, Two Wait States) Timings
Symbol
Parameter
Min (ns)
tCSLCSH
tAVCSL
tCSHAH
tRLRH
tRLDV1
Chip Select Low to Chip Select High Time
Address Valid to Chip Select Low
Address Hold after Chip Select High
Read Strobe Low to Read Strobe High Time
Read Strobe Low to Data Valid Time Standard
Read Mode
82.0
18.0
21.0
102.0
tRLDV2
Read Strobe Low to Data Valid Time Early Read
Mode
tCSLDV
tAVDV
tRHAH
tRHDH
tCSHDH
Chip Select Low to Data Valid
Address Valid to Data Valid
Address Hold after Read Strobe High
Data Hold after Read Strobe High
Data Hold after Chip Select High
1.0
0
18.0
Max (ns)
89.0
110.0
88.0
107.0
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