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PDF BS616LV1010EC Data sheet ( Hoja de datos )
| Número de pieza | BS616LV1010EC | |
| Descripción | Very Low Power/Voltage CMOS SRAM 64K X 16 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
64K X 16 bit
BS616LV1010
FEATURES
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV1010 is a high performance, very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
(ICCSB1, Max)
(ICC, Max)
Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V
PKG TYPE
BS616LV1010EC
BS616LV1010AC
+0 O C to +70 O C
2.4V ~ 5.5V
70
TSOP2-44
3uA
0.5uA
35mA
20mA
BGA-48-0608
BS616LV1010EI
BS616LV1010AI
-40 O C to +85 O C 2.4V ~ 5.5V
70
TSOP2-44
5uA
1.5uA
40mA
25mA
BGA-48-0608
PIN CONFIGURATIONS
BLOCK DIAGRAM
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
BS616LV1010EC
BS616LV1010EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
23456
A LB OE A0 A1 A2 NC
B
IO8 UB
A3
A4
CE
IO0
C IO9 IO10 A5 A6 IO1 IO2
D
VSS IO11 NC
A7
IO3 VCC
E VCC IO12 NC NC IO4 VSS
F
IO14 IO13 A14 A15
IO5 IO6
A8
A13
A15
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
18
Row
512
Decoder
DQ0
Data
16
Input
16
..
Buffer
..
..
16
..
Data
Output
16
DQ15
Buffer
Memory Array
512 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
G IO15 NC A12 A13 WE IO7
H
NC A8
A9 A10 A11 NC
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV1010
1
Revision 2.2
April 2001
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
t OH
t AA
t RC
BS616LV1010
t OH
CE
LB,UB
D OUT
t ACS
t BA
t (5)
CLZ
t BE
t tBDO
(5)
CHZ
READ CYCLE3 (1,4)
ADDRESS
t RC
t AA
OE
t OE
CE
LB,UB
t OLZ
t(5) ACS
t CLZ
t BA
t BE
D OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
t OH
t OHZ (5)
t (1,5)
CHZ
t BDO
R0201-BS616LV1010
5
Revision 2.2
April 2001
5 Page | ||
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| PDF Descargar | [ Datasheet BS616LV1010EC.PDF ] | |
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