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PDF BR93LC66 Data sheet ( Hoja de datos )
| Número de pieza | BR93LC66 | |
| Descripción | 4/096-Bit Serial Electrically Erasable PROM | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Memory ICs
4,096-Bit Serial Electrically Erasable PROM
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
•Features
• Low power CMOS Technology
• 256 × 16 bit configuration
• 2.7V to 5.5V operation
• Low power dissipation
– 3mA (max.) active current: 5V
– 5µA (max.) standby current: 5V
• Auto increment for efficient data bump
• Automatic erase-before-write
• Hardware and software write protection
– Default to write-disable state at power up
– Software instructions for write-enable / disable
– Vcc lockout inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages
• Device status signal during write cycle
• TTL compatible Input / Output
• 100,000 ERASE / write cycles
• 10 years Data Retention
•Pin assignments
CS 1
8 VCC NC 1
8 N.C.
SK 2
DI 3
7 N.C.
BR93LC66 /
BR93LC66RF
6 N.C.
VCC 2
CS 3
BR93LC66F /
BR93LC66FV
7 GND
6 DO
DO 4
5 GND SK 4
5 DI
•Pin descriptions
Pin
Name
Function
CS
SK
DI
DO
GND
N.C.
N.C.
VCC
Chip select input
Serial clock input
Start bit, operating code, address, and serial
data input
Serial data output, READY / BUSY internal
status display output
Ground
Not connected
Not connected
Power supply
•Overview
The BR93LC66 series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed
electrically. Each is configured of 256 words × 16 bits (4096 bits), and each word can be accessed individually and
data read from it and written to it.
Operation control is performed using five types of commands. The commands, addresses, and data are input
through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or
BUSY) can be output from the DO pin.
1
1 page  
Memory ICs
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
For low voltage operation (unless otherwise noted, Ta = – 40 to 85°C, VCC = 3V ± 10%)
Parameter
Symbol Min.
SK clock frequency
fSK —
SK "H" time
tSKH
1
SK "L" time
tSKL 1
CS "L" time
tCS 1
CS setup time
tCSS 200
DI setup time
tDIS 400
CS hold time
tCSH
0
DI hold time
tDIH 400
Data "1" output delay time
tPD1 —
Data "0" output delay time
tPD0 —
Time from CS to output confirmation
tSV —
Time from CS to output High impedance tDF —
Write cycle time
tE / W
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
250
—
—
—
—
—
—
—
2
2
2
400
25
Unit
kHz
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
ms
When reading at low voltage (Unless otherwise noted, Ta = – 40 to 85°C, VCC = 2.0V)
Parameter
Symbol Min.
SK clock frequency
fSK —
SK "H" time
tSKH
2
SK "L" time
tSKL 2
CS "L" time
tCS 2
CS setup time
tCSS 400
DI setup time
tDIS 800
CS hold time
tCSH
0
DI hold time
tDIH 800
Data "1" output delay time
tPD1 —
Data "0" output delay time
tPD0 —
Time from CS to output High impedance tDF
—
᭺ Not designed for radiation resistance.
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
200
—
—
—
—
—
—
—
4
4
800
Unit
kHz
µs
µs
µs
ns
ns
ns
ns
µs
µs
ns
5
5 Page 
Memory ICs
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
(6) Connecting DI and DO directly
The BR93LC66 have an independent input pin (DI) and
output pin (DO). These are treated as individual signals
on the timing chart but can be controlled through one
control line.
Control can be initiated on a single control line by
inserting a resistor R.
µ - COM
BR93LC66
I / O PORT
R
DI
DO
Fig.11 Common connections for
the DI and DO control line
1) Data collision between the µ-COM output and the
DO output
Within the input and output timing of the BR93LC66 the
drive from the µ-COM output to the DI input and a sig-
nal output from the DO output can be emitted at the
same time. This happens only for the 1 clock cycle (a
dummy bit “0” is output to the DO pin) which acquires
the AO address data during a read cycle. When the
address data AO = 1, the µ-COM output becomes a
direct current source for the DO pin.
The resistor R is the only resistance which limits this
current. Therefore, a resistor with a value which satis-
fies the µ-COM and the BR93LC66 current capacity is
required. When using a single control line, when a
dummy bit “0” is output to the DO, the µ-COM I / O
address data AO is also output. Therefore, the dummy
bit cannot be detected.
2) Feedback to the DI input from the DO output
Data is output from the DO pin and then feeds back
into the DI input through the resistor R. This happens
when:
• DO data is output during a read operation
• A READY / BUSY signal is output during WRITE or
WRAL operation
Such feedback does not cause problems in the basic
operation of the BR93LC66.
The µ-COM input level must be adequately maintained
for the voltage drop at R which is caused by the total
input leakage current for the µ-COM and the BR93LC-
66.
In the state in which SK is input, when the READY /
BUSY function is used, make sure that CS is dropped
to LOW within four clock pulses of the output of the
READY signal HIGH and the standby mode is restored.
For input after the fifth clock pulse, the READY HIGH
will be taken as the start bit and WDS or some other
mode will be activated, depending on the DI state.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet BR93LC66.PDF ] | |
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