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PDF BSP100 Data sheet ( Hoja de datos )
| Número de pieza | BSP100 | |
| Descripción | N-channel enhancement mode TrenchMOS transistor | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
N-channel enhancement mode
TrenchMOS™ transistor
Product specification
BSP100
FEATURES
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 30 V
ID = 6 A
RDS(ON) ≤ 100 mΩ (VGS = 10 V)
RDS(ON) ≤ 200 mΩ (VGS = 4.5 V)
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect transistor in a plastic
envelope
using
’trench’
technology.
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
The BSP100 is supplied in the
SOT223 surface mounting
package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
SOT223
4
123
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
Tsp = 25 ˚C
Tsp = 100 ˚C
Tamb = 25 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 65
MAX.
30
30
± 20
61
4.4
3.2
24
8.3
150
UNIT
V
V
V
A
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
Rth j-sp
Rth j-amb
PARAMETER
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
CONDITIONS
surface mounted, FR4
board
surface mounted, FR4
board
TYP.
12
70
MAX.
15
-
UNIT
K/W
K/W
1 Continuous current rating limited by package
February 1999
1
Rev 1.000
1 page  
Philips Semiconductors
N-channel enhancement mode
TrenchMOS™ transistor
Product specification
BSP100
1E-01
Sub-Threshold Conduction
1E-02
1E-03
min typ max
1E-04
1E-05
1E-06
01234
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
5
Capacitances, Ciss, Coss, Crss (pF)
1000
100
Ciss
Coss
Crss
10
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Source-Drain Diode Current, IF (A)
10
9 VGS = 0 V
8
7
6 150 C
5
4 Tj = 25 C
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A)
10
BSP100
25 C
Tj prior to avalanche =125 C
1
VDS
tp
ID
0.1
1E-06
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14 ID = 2.3A
13
12
Tj = 25 C
11 VDD = 15 V
10
9
8
7
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
February 1999
5
Rev 1.000
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet BSP100.PDF ] | |
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