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PDF BS62LV8000BI Data sheet ( Hoja de datos )
| Número de pieza | BS62LV8000BI | |
| Descripción | Very Low Power/Voltage CMOS SRAM 1M X 8 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
1M X 8 bit
BS62LV8000
FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
Vcc = 5V C-grade: 45mA (Max.) operation current
I -grade: 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max) at Vcc = 3V
-10 100ns (Max) at Vcc = 3V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
Vcc
TEMPERATURE RANGE
BS62LV8000EC
BS62LV8000BC
BS62LV8000EI
BS62LV8000BI
+0 O C to +70OC 2.4V ~ 5.5V
-40 O C to +85OC 2.4V ~ 5.5V
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS62LV8000EC
BS62LV8000EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12345
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
6
A NC OE A0 A1 A2 CE2
B NC NC A3 A4 CE1 NC
C
D0
NC A5
A6
NC D4
D VSS D1 A17 A7 D5 VCC
E VCC D2 VCC A16 D6 VSS
F D3 NC A14 A15 NC D7
G NC NC A12 A13 WE NC
GENERAL DESCRIPTION
The BS62LV8000 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable(CE2) and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8000 is available in 44 pin TSOP2 and 48-pin BGA type.
SPEED
( ns )
Vcc=3V
70 / 100
70 / 100
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC , Max )
PKG TYPE
Vcc=3V Vcc=5V Vcc=3V Vcc=5V
3uA
30uA
20mA
45mA
TSOP2-44
BGA-48-0810
6uA
100uA 25mA
50mA
TSOP2-44
BGA-48-0810
FUNCTIONAL BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 4096
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
4096
8 Column I/O
Write Driver
Sense Amp
8
512
Column Decoder
18
Address Input Buffer
A11A9 A8 A3 A2 A1 A0A10 A19
H
A18 A8
A9 A10 A11 A19
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV8000
1
Revision 2.4
April 2002
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
CE2
CE1
D OUT
t OH
t AA
t ACS2
t ACS1
t (5)
CLZ
t RC
READ CYCLE3 (1,4)
ADDRESS
OE
CE2
CE1
D OUT
t RC
t AA
t OE
t ACS2
t OLZ
t ACS1
t (5)
CLZ
BS62LV8000
t OH
t (5)
CHZ
t OH
t (5)
OHZ
t (1,5)
CHZ
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV8000
5
Revision 2.4
April 2002
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet BS62LV8000BI.PDF ] | |
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