PDF BS62LV2007HI Data sheet ( Hoja de datos )

Número de pieza	BS62LV2007HI
Descripción	Very Low Power/Voltage CMOS SRAM 256K X 8 bit
Fabricantes	Brilliance Semiconductor
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No Preview Available ! BSI Very Low Power/Voltage CMOS SRAM BS62LV2007 256K X 8 bit FEATURES • Wide Vcc operation voltage : 2.4V ~ 5.5V • Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current I- grade : 25mA (Max.) operating current 0.1uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 35mA (Max.) operating current I- grade : 40mA (Max.) operating current 0.6uA (Typ.) CMOS standby current • High speed access time : -70 70ns(Max.) at Vcc = 3.0V -10 100ns(Max.) at Vcc = 3.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE2, CE1, and OE options DESCRIPTION The BS62LV2007 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates in a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.1uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV2007 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2007 is available in the JEDEC standard 36 pin Mini BGA 6x8 mm. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE BS62LV2007HC BS62LV2007HI 0 O C to +70 O C -40 O C to +85 O C 2.4V ~5.5V SPEED (ns) Vcc= 3.0V 70/100 70/100 POWER DISSIPATION STANDBY Operating (ICCSB1, Max) (ICC, Max) Vcc= 5.0V Vcc= 3.0V Vcc= 5.0V Vcc= 3.0V 6 uA 0.7 uA 35 mA 20 mA 25 uA 1.5 uA 40 mA 25 mA PKG TYPE BGA-36- 0608 PIN CONFIGURATIONS BLOCK DIAGRAM A13 A17 A15 A16 A14 A12 A7 A6 A5 A4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 CE2 WE OE Vdd Gnd Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048 8 8 Control Data Input Buffer Data Output Buffer 2048 8 Column I/O Write Driver Sense Amp 8 256 Column Decoder 16 Address Input Buffer A11 A9 A8 A3 A2 A1 A0 A10 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS62LV2007 1 Revision 2.0 April 2002 1 page BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) ADDRESS D OUT t OH t AA t RC BS62LV2007 t OH READ CYCLE2 (1,3,4) CE1 t ACS1 CE2 D OUT READ CYCLE3 (1,4) ADDRESS OE CE1 CE2 D OUT t ACS2 t (5) CLZ t RC t AA t OE t OLZ t ACS1 t (5) CLZ1 t ACS2 t (5) CLZ2 NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. t , tCHZ1 (5) CHZ2 t OH t (5) OHZ t (1,5) CHZ1 t (2,5) CHZ2 R0201-BS62LV2007 5 Revision 2.0 April 2002 5 Page

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