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PDF BUK7505-30A Data sheet ( Hoja de datos )

Número de pieza BUK7505-30A
Descripción TrenchMOS transistor Standard level FET
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
TrenchMOStransistor
Standard level FET
Product specification
BUK7505-30A
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope using
trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
general purpose switching
applications.
PINNING - TO220AB
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 10 V
MAX.
30
75
230
175
5
PIN CONFIGURATION
SYMBOL
d
tab
1 23
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
RGS = 20 k
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
Minimum footprint, FR4
board
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
20
75
75
400
230
175
TYP.
-
50
MAX.
0.65
-
UNIT
V
A
W
˚C
m
UNIT
V
V
V
A
A
A
W
˚C
UNIT
K/W
K/W
September 1999
1
Rev 1.100

1 page




BUK7505-30A pdf
Philips Semiconductors
TrenchMOStransistor
Standard level FET
Product specification
BUK7505-30A
VGS(TO) / V
5
max.
4
typ.
3
min.
2
BUK759-60
1
-0100
-50
0 50
Tj / C
100 150 200
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ
98%
1E-04
1E-05
1E-06
01234
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
5
10
9
8
7
6
5
4 Ciss
3
2
Coss
1 Crss
0
0.01 0.1
1 VDS/V 10
100
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
12
VGS/V
10
8
VDS = 14V
24V
6
4
2
0
0 20 40 60 80 100 120 140
QG/nC
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 50 A; parameter VDS
100
ID/A
80
60
Tj/C = 175
25
40
20
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
VSDS/V
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.16. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
September 1999
5
Rev 1.100

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