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Número de pieza | BUK565-60H | |
Descripción | PowerMOS transistor Logic level FET | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de BUK565-60H (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! Philips Semiconductors
PowerMOS transistor
Logic level FET
Product specification
BUK565-60H
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in
a plastic envelope suitable for
surface mount applications.
The device is intended for use in
automotive and general purpose
switching applications.
PINNING - SOT404
PIN DESCRIPTION
1 gate
2 drain
3 source
mb drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
VGS = 5 V
MAX.
60
41
125
175
38
PIN CONFIGURATION
SYMBOL
d
mb
2
13
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
±VGSM
ID
ID
IDM
Ptot
Tstg
Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source
voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
-
RGS = 20 kΩ
-
tp ≤ 50 µs
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
-
MIN.
-
-
-
-
-
-
-
-
- 55
-
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
minimum footprint, FR4 board
(see Fig. 18)
MAX.
60
60
15
20
41
29
164
125
175
175
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
TYP. MAX. UNIT
- 1.2 K/W
50 - K/W
June 1995
1
Rev 1.000
1 page Philips Semiconductors
PowerMOS transistor
Logic level FET
Product specification
BUK565-60H
VGS / V
15
10
5
BUK5Y5-60H
VDD / V = 12
48
0
0 10 20 30 40 50 60 70 80
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 41 A; parameter VDS
IS / A
100
Tj / C =
80
-40
25
150
60
BUKXY5-60H
40
20
0
0 0.5 1 1.5
VSDS / V
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 41 A
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS/(BVDSS − VDD)
June 1995
5
Rev 1.000
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet BUK565-60H.PDF ] |
Número de pieza | Descripción | Fabricantes |
BUK565-60A | PowerMOS transistor Logic level FET | NXP Semiconductors |
BUK565-60H | PowerMOS transistor Logic level FET | NXP Semiconductors |
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