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PDF M5K4164ANP-20 Data sheet ( Hoja de datos )
| Número de pieza | M5K4164ANP-20 | |
| Descripción | 64K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
MSK4164ANP-20
6SS36-BIT (6SS36-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 65536-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
uSe of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities. The
M5K4164ANP operates on a 5V power supply using the
on-chip substrate bias generator.
FEATURES
Type name
M5K4164ANP-20
Access time
(maxi
(nsl
200
Cycle time
(mini
(ns)
330
Power dissipation
(typl
(mWI
125
• Single 5V±20/ supply
• Low standby power dissipation: 22.0 mW (max)
• Low operating power dissipation: 225 mW (max)
• Unlatched output enables two-dimensional chip selec-
tion and extended page boundary
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only refresh, and page-mode
capabilities
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-stage and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
PIN CONFIGURATION (TOP VIEW)
NC'" 1
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS RAS -+ 4
STROBE INPUT
ADDRESS
INPUTS
(5V) Vee
Vss (OV)
15 +- CAS ~~~g~~ 1~~~fESS
DATA OUTPUT
ADDRESS
INPUTS
Outline 16P4
• CAS controlled output allows hidden refresh.
• Output data can be held infinitely by CAS.
• Interchangeable with intel's 2164 and Motorola's MCM
6665 in pin configuration.
APPLICATION
• Main memory unit for computers.
BLOCK DIAGRAM
DATA INPUT D 2 )-----------'---------~_;:::::J~~
WRITE CONTROL INPUT W 3 } - - - - - - - - - - - - - - < : 1
COL~~R~~tP?~$0¥
ROW ADDRESS
STROBE INPUT
COLUMN DECODER
MEMORY CELL
164 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
MEMORY CELL
164 ROWS X 256 COLUMNSI
COLUMN DECODER
ADDRESS INPUTS
MEMORY CELL
164 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
164 ROMWESMXOR2Y56CCEOLLUMNS)
COLUMN DECODE R
Vee< 5V)
14 Q DATA OUTPUT
J'
--
2-24
•. MITSUBISHI
.... ELECTRIC
1 page  
MITSUBISHI LSls
MSK4164ANP-20
6SS36-BIT (6SS36-WORD BY I-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =0 -70°C. Vcc= 5 v ± 10%. v 55 =OV. unless otherwise noted, See notes 5, 6 and 7)
Symbol
Parameter
Alternative
Symbol
M5K4164ANP-20
Limits
Min Max
Unit
IORF
I W(RASH)
IW(RASL)
I W(CASL)
I W(CASH)
I h (RAS-CAS)
I h (CAS-RAS)
Id (CAS-RAS)
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RAS
(NoteS)
(Note 9)
IREF
IRP
I RAS
ICAS
ICPN
ICSH
I RSH
ICRP
120
200
100
40
200
100
-20
2
10000
00
ms
ns
ns
ns
ns
ns
ns
ns
Id(RAS-CAS)
ISU(RA-RAS)
Oelay time. RAS to CAS
Row address setup tim~ before RAS
(Note 101
I RCD
I ASR
30
0
100 ns
ns
I su (CA- CAS)
Ih(RAS-RA)
Column address setup time before CAS
Row address hold time after RAS
I ASC
I RAH
0
25
ns
ns
Ih(CAS-CA)
Column address hold time after CAS
I CAH
35
ns
I h (RAS-CA)
Column address hold time after RAS
I AR 120
ns
I THL
I TLH
Transition time
IT 3
50 ns
Note 5·
An
initial
pause of 500.us is required after power-up
followed
by a.ny eight
-
AAS
or
-AAS-/C-AS
cycles
before
proper
device
operation
is achieved_
The switching characteristics are defined as t THL = t TLH =5ns,
7 Reference levels of input signals are VIH min. and Vil max. Reference levels for tranSition time; are also between ViH and VI L.
8: Except for page·mode.
td(CAS-RASI requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS)
10' Operation within the td (RAS-CAS) max limit insures that t a eRAS) max can be met. td (RAS-CAs)max is specified reference point only;if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit, then access time is controlled exclusively by ta (CAS),
I d (RAS- CAs)mln = Ih (RAS-RA) min + 2 I THL(t TLH) + I su (CA-CAS)mln_
SWITCHING CHARACTERISTICS (Ta=0-70'C, Vcc=5V±10%, Vss=OV, unlessotherwisenoted)
Read Cycle
Symbol
leR
Isu (R-CAS)
Ih (cAS-R)
Ih (RAS-R)
Idls (cAS)
la (CAS)
.la(RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access ti me
RAS access time
(Note 111
(Note 111
(Note 121
(Note 131
(Note 141
Alternative
Symbol
I RC
I RCS
I RCH
IRRH
IOFF
I CAC
I RAC
M5K4164ANP-20
Limits
Min Max
330
0
0
25
0 50
100
200
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11
Note 12
Note 13:
Note 14:
Either th (RAS-R) or th (CAS-A) must be satisfied for a read cycle.
tdIS(CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL.
This is the value when·td (RAS-CAS)~td (RAS-CAS)max. Test conditions; Load == 2T TL, CL = 100pF
This is the value when td (RAS-CAS)< td (RAS-CAs)max. When t d (RAS-CAS)~ td (RAS-CAS)maX, ta (RAS) will increasp by the amount that
td (RAS-CAS) exceeds the value shown Test conditions; Load = 2T Tl, CL = 100pF
Write Cycle
Symbol
Parameter
low
Isu (W-CAS)
Ih (CAS-W)
Ih (RAS-W)
Ih (W-RAS)
Ih (W-CAS)
Iw(w)
Isu (D-CAS)
Ih (cAS-D)
Ih (RAS-D)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Write pulse width
Data-in setup time before CAS
Data-in hold time after CAS
Data-in hold time after RAS
INote 171
Alternative
Symbol
I RC
I WCS
IWCH'
I WCR
I RWL
ICWL
Iwp
los
I DH
I DHR
M5K4164ANP-20
Limits
Min Max
330
-10
55
120
55
55
55
0
55
120
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-28
• MITSUBISHI
"ELECTRIC
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