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PDF CY8C3866 Data sheet ( Hoja de datos )
| Número de pieza | CY8C3866 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
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PSoC® 3: CY8C38 Family Datasheet
Programmable System-on-Chip (PSoC®)
General Description
PSoC® 3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a
microcontroller on a single chip. The PSoC 3 architecture boosts performance through:
8051 core plus DMA controller and digital filter processor, at up to 67 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Voltage range: 1.71 to 5.5 V, up to six power domains
Temperature range (ambient) –40 to 85 °C[1]
DC to 67-MHz operation
Power modes
• Active mode 1.2 mA at 6 MHz, and 12 mA at 48 MHz
• 1-µA sleep mode
• 200-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Performance
8-bit 8051 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
24-bit 64-tap fixed-point digital filter processor (DFB)
Memories
Up to 64 KB program flash, with cache and security features
Up to 8 KB additional flash for error correcting code (ECC)
Up to 8 KB RAM
Up to 2 KB EEPROM
Digital peripherals
Four 16-bit timer, counter, and PWM (TCPWM) blocks
I2C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral
interface (TID#40770053) using internal oscillator[2]
Full CAN 2.0b, 16 Rx, 8 Tx buffers
16 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I2C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
Programmable clocking
3- to 62-MHz internal oscillator, 1% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 67 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
Analog peripherals
Configurable 8- to 20-bit delta-sigma ADC
Up to four 8-bit DACs
Up to four comparators
Up to four opamps
Up to four programmable analog blocks, to create:
• Programmable gain amplifier (PGA)
• Transimpedance amplifier (TIA)
• Mixer
• Sample and hold circuit
CapSense® support, up to 62 sensors
1.024 V ±0.1% internal voltage reference
Versatile I/O system
29 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Programming and debug
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Bootloader programming through I2C, SPI, UART, USB, and
other interfaces
Package options: 48-pin SSOP, 48-pin QFN, 68-pin QFN,
100-pin TQFP, and 72-pin WLCSP
Development support with free PSoC Creator™ tool
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free Keil 8051 compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See Ordering Information on page 123 for details.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-11729 Rev. AF
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 27, 2016
1 page  
PSoC® 3: CY8C38 Family Datasheet
For more details on the peripherals see the “Example
Peripherals” section on page 44 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 44 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
Analog-to-digital converter (ADC)
Digital-to-analog converters (DACs)
Digital filter block (DFB)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±2 LSB
DNL less than ±1 LSB
SINAD better than 84 dB in 16-bit mode
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
The output of the ADC can optionally feed the programmable
DFB through the DMA without CPU intervention. You can
configure the DFB to perform IIR and FIR digital filters and
several user-defined custom functions. The DFB can implement
filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high-speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths. In addition
to the ADC, DACs, and DFB, the analog subsystem provides
multiple:
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the “Analog Subsystem” section on page 56 of this data
sheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 67 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an error
correcting code (ECC) for high reliability applications. A powerful
and flexible protection model secures the user's sensitive
information, allowing selective memory block locking for read
and write protection. Up to 2 KB of byte-writeable EEPROM is
available on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive[3], CapSense[4], flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow VOH to be set independently of Vddio when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All of the features of the PSoC I/Os are
covered in detail in the “I/O System and Routing” section on
page 37 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the clock base for the
system, and has 1-percent accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
clock frequencies up to 67 MHz from the IMO, external crystal,
or external reference clock.
Notes
3. This feature on select devices only. See Ordering Information on page 123 for details.
4. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-11729 Rev. AF
Page 5 of 140
5 Page 
PSoC® 3: CY8C38 Family Datasheet
Figure 2-7. Example Schematic for 100-pin TQFP Part with Power Connections
VDDD
VDDD
VDDD
C6
0.1uF
VSSD
C1
1uF
VSSD
C2
0.1uF
VCCD
VSSD
VSSD
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
VDDIO0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
OA1OUT, P3[6]
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
VDDA
C8
0.1uF
C17
1uF
VSSD
VSSA
VSSD
VDDA
VSSA
VCCA
VDDA
C9 C10
1uF 0.1uF
VSSA
VDDD
C12
0.1uF
VSSD
C16
0.1uF
C15
1uF
VDDD
C11
0.1uF
VSSD
VSSD
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-8 on page 12.
For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-3-cad-libraries.
Document Number: 001-11729 Rev. AF
Page 11 of 140
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C3866.PDF ] | |
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