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PDF ADuC7023 Data sheet ( Hoja de datos )

Número de pieza ADuC7023
Descripción Precision Analog Microcontroller
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
Precision Analog Microcontroller, 12-Bit Analog
I/O, ARM7TDMI MCU with Enhanced IRQ Handler
ADuC7023
FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 12 ADC channels
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
4 DAC outputs available
On-chip voltage reference
On-chip temperature sensor
Voltage comparator
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
On-chip peripherals
2× fully I2C-compatible channels
SPI (20 Mbps in master mode, 10 Mbps in slave mode)
With 4-byte FIFO on input and output stages
Up to 20 GPIO pins—Digital only GPIOs are 5 V tolerant
3× general-purpose timers
Watchdog timer (WDT)
Programmable logic array (PLA)
16 PLA elements
16-bit, 5-channel PWM
Power
Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 28 mA at 41.78 MHz
Packages and temperature range
32-lead 5 mm × 5 mm LFCSP
40-lead LFCSP
36-Lead WLCSP
Fully specified for −40°C to +125°C operation
Tools
Low cost QuickStart development system
Full third-party support
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
APPLICATIONS
Optical networking
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems
GENERAL DESCRIPTION
The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data acquisition
system, incorporating high performance multichannel ADCs,
16-bit/32-bit MCUs, and Flash/EE memory on a single chip.
The ADC consists of up to 12 single-ended inputs. An additional four
inputs are available but are multiplexed with the four DAC output
pins. The ADC can operate in single-ended or differential input modes.
The ADC input voltage is 0 V to VREF. A low drift band gap reference,
temperature sensor, and voltage comparator complete the ADC
peripheral set.
The DAC output range is programmable to one of two voltage ranges.
The DAC outputs have an enhanced feature of being able to retain
their output voltage during a watchdog or software reset sequence.
The devices operate from an on-chip oscillator and a PLL, generating
an internal high frequency clock of 41.78 MHz. This clock is routed
through a programmable clock divider from which the MCU core
clock operating frequency is generated. The microcontroller core is an
ARM7TDMI®, 16-bit/32-bit RISC machine that offers up to 41 MIPS
peak performance. Eight kilobytes of SRAM and 62 kilobytes of
nonvolatile Flash/EE memory are provided on chip. The ARM7TDMI
core views all memory and registers as a single linear array.
The ADuC7023 contains an advanced interrupt controller. The
vectored interrupt controller (VIC) allows every interrupt to be
assigned a priority level. It also supports nested interrupts to a
maximum level of eight per IRQ and FIQ. When IRQ and FIQ
interrupt sources are combined, a total of 16 nested interrupt
levels are supported.
On-chip factory firmware supports in-circuit download via the I2C
serial interface port, and nonintrusive emulation is supported via
the JTAG interface. These features are incorporated into a low cost
QuickStart™ development system supporting this MicroConverter®
family. The part contains a 16-bit PWM with five output signals.
For communication purposes, the part contains 2 × I2C channels that
can be individually configured for master or slave mode. An SPI
interface supporting both master and slave modes is also provided.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. The ADuC7023 is
available in either a 32-lead or 40-lead LFCSP package. A 36-ball
wafer level CSP package (WLCSP) is also available.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADuC7023 pdf
ADuC7023
6/10—Rev. 0 to Rev. A
Changes to Temperature Sensor Parameter in Table 1................ 6
Changes to Table 24........................................................................ 29
Changes to Temperature Sensor Section ..................................... 34
Changes to DACBKEY0 Register Section and to Table 43 ....... 47
Changes to Ordering Guide .......................................................... 93
1/10—Revision 0: Initial Version
Data Sheet
Rev. G | Page 4 of 97

5 Page





ADuC7023 arduino
ADuC7023
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter
Description
tSL SCLK low pulse width1
tSH SCLK high pulse width1
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge1
tDHD Data input hold time after SCLK edge1
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
1 × tUCLK
2 × tUCLK
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
Typ
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
5
5
5
5
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI
tSH
tSL
tDAV
tDF
MSB
tSR
tDR
BIT 6 TO BIT 1
tSF
LSB
MISO
MSB IN
BIT 6 TO BIT 1
tDSU
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
LSB IN
Data Sheet
Max Unit
ns
ns
25 ns
ns
ns
12.5 ns
12.5 ns
12.5 ns
12.5 ns
Rev. G | Page 10 of 97

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