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PDF SI7615ADN Data sheet ( Hoja de datos )
| Número de pieza | SI7615ADN | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Vishay | |
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New Product
P-Channel 20-V (D-S) MOSFET
Si7615ADN
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) () Max.
0.0044 at VGS = - 10 V
- 20 0.0060 at VGS = - 4.5 V
0.0098 at VGS = - 2.5 V
ID (A)
- 35a
- 35a
- 35a
Qg (Typ.)
59 nC
PowerPAK® 1212-8
3.3 mm
S
1S
3.3 mm
2
S
3G
4
D
8D
7
D
6
D
5
Bottom View
Ordering Information:
Si7615ADN-T1-GE3 (Lead (Pb)-free and Halogen-free)
FEATURES
• TrenchFET® Gen III P-Channel Power MOSFET
• 100 % Rg and UIS Tested
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
APPLICATIONS
• Adaptor Switch
• Battery Switch
• Load Switch
S
G
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current (t = 300 µs)
Continuous Source-Drain Diode Current
Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
TC = 25 °C
TA = 25 °C
L = 0.1 mH
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
VDS
VGS
ID
IDM
IS
IAS
EAS
PD
TJ, Tstg
Limit
- 20
± 12
- 35a
- 35a
- 22.1b, c
- 17.6b, c
- 80
- 35a
- 3.3b, c
- 20
20
52
33
3.7b, c
2.4b, c
- 55 to 150
260
Unit
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
RthJA
RthJC
26
1.9
33
°C/W
2.4
Notes:
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 81 °C/W.
Document Number: 62667
For technical questions, contact: [email protected]
www.vishay.com
S12-1262-Rev. A, 21-May-12
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
New Product
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
Si7615ADN
Vishay Siliconix
80
60
40 Limited by Package
20
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Current Derating*
65 2.0
52 1.6
39 1.2
26 0.8
13 0.4
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power Derating, Junction-to-Case
0.0
0
25 50 75 100 125 150
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Ambient
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 62667
For technical questions, contact: [email protected]
www.vishay.com
S12-1262-Rev. A, 21-May-12
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
AN822
Vishay Siliconix
105
Spreading Copper (sq. in.)
95
85
75
65
55
0%
45
100 %
50 %
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN
130
120 Spreading Copper (sq. in.)
110
100
90
80
50 %
100 %
70
60 0 %
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor-
mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attrac-
tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
www.vishay.com
4
Document Number 71681
03-Mar-06
11 Page | ||
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