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PDF TSE2004GB2B0 Data sheet ( Hoja de datos )
| Número de pieza | TSE2004GB2B0 | |
| Descripción | DDR4 Temperature Sensor | |
| Fabricantes | IDT | |
| Logotipo |  |
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DDR4 Temperature Sensor with
Integrated 4Kbit EEPROM for
® Memory Modules
TSE2004GB2B0
Data Sheet
Description
The TSE2004GB2B0 digital temperature sensor with accuracy up to
±0.5°C was designed to target applications demanding highest level of
temperature readout. The device also contains 512 Byte EEPROM for
storage of vendor information and system configuration such as SPD for
DIMM modules. The sensor and the EEPROM are fully compliant with
JEDEC JC42.4 Component Specification.
The digital temperature sensor comes with several user-programmable
registers to provide maximum flexibility for temperature-sensing
applications. The registers allow specifying critical, upper, and lower
temperature limits as well as hysteresis settings. Both the limits and
hysteresis values are used for communicating temperature events from
the chip to the system. This communication is done using Event pin,
which has an open-drain configuration. The user has the option of setting
the Event pin polarity as either an active-low or active-high comparator
output for thermostat operation, or as a temperature event interrupt
output for microprocessor-based systems.
The sensor uses an industry standard 2-wire, I2C/SMBus serial
interface, and allows up to eight devices to be controlled on the bus.
The 4Kbit (512 Bytes) serial EEPROM memory in the part is organized
as two pages of 256 bytes each, or 512 bytes of total memory. Each page
is comprised of two 128 byte blocks. The devices are able to selectively
lock the data in any or all of the four 128-byte blocks.
Memory Module Temp Sensor Application
Memory
Module
CPU
Chipset
(for memory
throttling)
EVENT#
SMBus
DRAMs
Temperature
sensor and
EEPROM
MCH
Memory Bus
DRAMs
Features
• Temperature Sensor + 512 Byte Serial EEPROM
• 512 Byte Serial EEPROM for SPD
• Single Supply: 2.2V to 3.6V
• Accurate timeout support
- Meets strict SMBus spec of 25ms (min), 35ms (max)
• Timeout supported for Temp Sensor and EEPROM
• Timeout supported in all Modes
– Active mode for Temp sensor and EEPROM
– EEPROM in standby or Temp sensor in shutdown
– EEPROM in standby and Temp sensor in shutdown
• Schmitt trigger and noise filtering on bus inputs
• 2-wire Serial Interface: 10KHz to 1 MHz max I2C™ /SMBus™
• Available Package: TDFN-8
Temperature Sensor Features
• Temperature Converted to Digital Data
• Sampling Rate of 125ms (max)
• Selectable 0, 1.5°C, 3°C, 6°C Hysteresis
• Programmable Resolution from 0.0625°C to 0.5°C
• Accuracy:
– ±0.5°C/ ±1.0°C (typ/max)from +75°C to +95°C
– ±1.0°C/±2.0°C (typ/max) from +40°C to +125°C
– ±2.0°C/ ±3.0°C (typ/max) from -40°C to +125°C
Serial EEPROM Features
• Individual Reversible Software Data Protection for all 128 Byte
Blocks
• Byte and page (up to 16 Bytes) Write Operation
• Self-time Write cycle
• Automatic address incrementing
• Random and Sequential Read modes
Typical Applications
• DIMM Modules (DDR3, DDR4)
• Servers, Laptops, Ultra-portables, PCs, etc.
• Industrial temperature monitors
• Hard Disk Drives and Other PC Peripherals
2014 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 31
*Notice: The information in this document is subject to change without notice
September 16, 2014
DSC 7340/4
1 page  
DC Characteristics
ILI
ILO
IDD
IDD1
VIL
VIH
VHV
VOL1
IOL
VHYST
VPON
VPOFF
Notes:
Parameter
Conditions
Input leakage current
(SCL, SDA)
Output leakage
current
Supply current
Standby Supply
current
Input low voltage
(SCL, SDA)
Input high voltage
(SCL, SDA)
SA0 high voltage
Output low voltage
open-drain or
open-collector
LOW-level output
current1
VIN = VSSSPD or VDDSPD
VOUT = VSSSPD or
VDDSPD, SDA in Hi-Z
VDDSPD = 3.3 V, fC = 100
kHz (rise/fall time < 30 ns)
VIN = VSSSPD or VDDSPD,
VDDSPD = 3.6 V
VIN = VSSSPD or VDDSPD,
VDDSPD = 2.2V
--
--
VHV - VDDSPD > 4.8 V
3 mA sink current,
VDDSPD > 2 V
VOL = 0.4 V
VOL = 0.6 V
Input hysteresis
Power On Reset
threshold
Power Off threshold
for warm power on
cycle
VDDSPD > 2 V
Monotonic rise between
VPON and VDDSPD(min)
without ringback
No ringback above VPOFF
f < 400KHz
Min Max
-- ± 5
-- ± 5
-- 2
-- 100
-- 100
-0.5
0.7 *
VDDSPD
7
--
0.3 *
VDDSPD
VDDSPD
+ 0.5
10
0.4
3
6
0.05 *
VDDSPD
1.6
--
--
-- 0.9
f > 400 KHz
Min Max
-- ± 5
-- ± 5
Units
A
A
-- 2 mA
-- 100 A
-- 100 A
-0.5
0.7 *
VDDSPD
7
--
0.3 *
VDDSPD
VDDSPD
+ 0.5
10
0.4
V
V
V
V
20
--
0.05 *
VDDSPD
1.6
mA
mA
-- V
-- V
-- 0.9 V
1. In order to drive full bus load at 400 KHz, 6 mA IOL is required at 0.6 V VOL. Parts not meeting this specification can still function, but not
at 400 KHz and 400 pF.
5 of 31
*Notice: The information in this document is subject to change without notice
September 16, 2014
5 Page 
Device Diagram
Device Interface
The TSE2004GB2B0 behaves as a slave device in the I2C Bus protocol, with all memory operations synchronized by the serial clock. Read and
Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and
R/W# bit (as described in the I2C Bus Operating Mode table), terminated by an acknowledge bit. The TSE2004GB2B0 does not initiate clock
stretching which is an optional I2C Bus feature.
In accordance with the I2C Bus definition, the device uses three (3) built-in, 4-bit Device Type Identifier Codes (DTIC) and the state of SA0, SA1,
and SA2 to generate an I2C Bus Slave Address. The SPD memory may be accessed using a DTIC of (1010), and to perform the SWPn, RSPn, or
CSWP operations a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011).
Serial Address Selection
Inputs SA0, SA1, and SA2 inputs are directly combined with the DTIC and the EE page address bit to qualify SMBus addresses. Each of the SA
pins is tied to VDDSPD or VSSSPD and the Logical Serial Address (LSA) is equal to the code on the Serial Address pins.
I2C Bus Addressing Modes
Logical Serial Address(LSA)
SA2
000 0
001 0
010 0
011 0
100 1
101 1
110 1
111 1
Note 1: 0 = VSSSPD, 1 = VDDSPD
SA1
0
0
1
1
0
0
1
1
SA0
0
1
0
1
0
1
0
1
11 of 31
*Notice: The information in this document is subject to change without notice
September 16, 2014
11 Page | ||
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| PDF Descargar | [ Datasheet TSE2004GB2B0.PDF ] | |
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