|
|
PDF MN101EF57G Data sheet ( Hoja de datos )
| Número de pieza | MN101EF57G | |
| Descripción | 8-bit Single-chip Microcontroller | |
| Fabricantes | Panasonic | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MN101EF57G (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
MN101E56/57/76 Series
8-bit Single-chip Microcontroller
Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate multiple types
of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air
conditioner, PPC, fax machine, music instrument and other applications.
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a simple efficient instruction
set. MN101EF57 series has an internal 128 KB of ROM and 6 KB of RAM. Peripheral functions include 5 external interrupts, 29 internal
interrupts including NMI, 12 timer counters, 4 types of serial interfaces, A/D converter, D/A converter, LCD driver, 2 types of watchdog
timer, data automatic function and buzzer output. The system configuration is suitable for in camera, timer selector for VCR, CD player, or
minicomponent.
With 5 oscillation systems (high-speed (internal frequency: 20 MHz), high-speed (crystal/ceramic frequency: max. 10 MHz) / low-speed
(internal frequency: 30 kHz), low-speed (crystal/ceramic frequency: 32.768 kHz) and PLL: frequency multiplier of high frequency) contained
on the chip, the system clock can be switched to high-speed frequency input (NORMAL mode), PLL input (PLL mode), or to low-speed
frequency input (SLOW mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for the
system can be selected by switching its frequency ratio by programming. High speed mode has the normal mode which is based on the clock
dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2), and the double speed mode which is based on the clock not
dividing fpll.
A machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original oscillation fosc is 10 MHz (PLL is not
used). A machine cycle in the double speed mode, in which the CPU operates on the same clock as the external clock, is 100 ns when fosc is
10 MHz. A machine cycle in the PLL mode is 50 ns (maximum).
Product Summary
This datasheet describes the following model.
Model
ROM Size
MN101EF76K
256 KB
RAM Size
10 KB
Classification
MN101EF57G
128 KB
6 KB
Flash EEPROM version
MN101EF56K
256 KB
10 KB
Note) DMOD internal pull-up resistor is in only Flash EEPROM version.
When using In-circuit Emulator, it is necessary to connect the pull-up resistor on the circuit board.
Package
LQFP128-P-1818C
LQFP080-P-1414A
TQFP080-P-1212F
QFP100-P-1818B
Publication date: February 2014
Ver. BEM
1
1 page  
MN101E56/57/76 シリーズ
Features (continued)
Timer Counter (continued)
Timer 6 (8-bit free-run timer, time-base timer)
8-bit free-run timer
Clock source:
fpll-div, fpll-div/22, fpll-div/23, fpll-div/212, fpll-div/213, fs, fslow, fslow/22, fslow/23, fslow/212, fslow/213
Time-base timer
Interrupt generation cycle:
fpll-div/27, fpll-div/28, fpll-div/29, fpll-div/210, fpll-div/213, fpll-div/215, fslow/27, fslow/28, fslow/29, fslow/210, fslow/213,
fslow/215
Timer 7 (General-purpose 16-bit timer)
Clock source:
fpll-div, fs, external clock, timer A output, serial 0 transfer clock output, timer 6 compare match cycle divided by 1, 2, 4, 16
Hardware configuration:
Double-buffered compare register (×2)
Double-buffered input capture register (×2)
Timer interrupt (×2 vector)
Timer function:
Square wave output (Timer pulse output), high-precision PWM output (cycle/duty continuous changeable) can be output to large
current pin TM7IOB, timer synchronous output, event count, input capture function (both edges operable)
Real-time control:
Timer (PWM) output is controlled among the three values: "Fixed to High", "Fixed to Low", or "Hi-Z" at falling edge of external
interrupt 0 (IRQ0)
Timer 8 (General-purpose 16-bit timer)
Clock source:
fpll-div, fs, external clock, timer A output, timer 6 compare match cycle divided by 1, 2, 4, 16
Hardware configuration:
Double-buffered compare register (×2)
Double-buffered input capture register (×1)
Timer interrupt (×2 vector)
Timer function:
Square wave output (Timer pulse output), high-precision PWM output (cycle/duty continuous changeable) can be output to large
current pin TM8IOB, event count, pulse width measurement, input capture function (both edges operable)
32-bit cascade connection (connected with timer 7), 32-bit PWM output, input capture is available in 32-bit cascade
Timer 9 (Motor control 16-bit timer)
Clock source:
fpll-div, fs, external clock, Timer A output divided by 1, 2, 4, 16
Hardware configuration:
Double-buffered compare register (×2)
Timer interrupt (×3 vector)
Timer function:
Square wave output (Timer pulse output) can be changed to large current output, complementary
3-phase PWM output, triangle wave and saw tooth wave are supported, dead time insertion available, event count
Pin output control:
PWM output control is possible by external interrupt 0 to 4 (IRQ 0 to 4) ("Hi-z", output data fixed)
Timer A (baud rate timer)
Clock output for peripheral functions
Clock source:
fpll-div divided by 1/1, 2, 4, 8, 16, 32, and fs divided by 2, 4
Ver. BEM
5
5 Page 
MN101E56/57/76 シリーズ
Pin Description (continued)
MN101EF57G (LQFP080-P-1414A, TQFP080-P-1212F)
TM0IOA/AN0/SEG38/PA0
1
60 P52/SEG17/SBT1A
TM1IOA/AN1/SEG39/PA1
2
59 P51/SEG16/SBI1A/RXD1A
TM2IOA/AN2/SEG40/PA2
3
58 P50/SEG15/SBO1A/TXD1A
TM3IOA/AN3/PA3
4
57 P62/SEG14/TM1IOB
TM4IOA/AN4/PA4
5
56 P63/SEG13/TM3IOB
TM7IOA/AN5/PA5
6
55 P64/SEG12/TM4IOB
TM8IOA/AN6/PA6
7
54 P65/SEG11/SBO2A/TXD2A
TM9IOA/AN7/PA7
8
53 P66/SEG10/SBI2A/RXD2A
VREF+
ATRST
NRST/P27
9
10
11
MN101EF57G
(80LQFP/TQFP Top View)
52
51
50
P67/SEG9/SBT2A
P70/SEG8/KEY0/SBI4A
P71/SEG7/KEY1/SBO4A/SDA4A
XI/P90
12
49 P72/SEG6/KEY2/SBT4A/SCL4A
XO/P91
13
48 P73/SEG5/KEY3
VSS 14
47 P74/SEG4/KEY4
OSC1/P25
15
46 P75/SEG3/KEY5/SBO1B/TXD1B
OSC2/P26
16
45 P76/SEG2/KEY6/SBI1B/RXD1B
VDD5
17
44 P77/SEG1//KEY7/SBT1B
MMOD
18
43 P80/SEG0/SDO0/TM9OD0
VDD18
19
42 P81/COM0/SDO1/TM9OD1
DMOD
20
41 P82/COM1/SDO2/TM9OD2
Ver. BEM
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MN101EF57G.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MN101EF57G | 8-bit Single-chip Microcontroller | Panasonic |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |