|
|
PDF SIC530 Data sheet ( Hoja de datos )
| Número de pieza | SIC530 | |
| Descripción | Integrated Power Stage | |
| Fabricantes | Vishay | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SIC530 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
www.vishay.com
SiC530
Vishay Siliconix
30 A VRPower® Integrated Power Stage
DESCRIPTION
The SiC530 is an integrated power stage solution optimized
for synchronous buck applications to offer high current, high
efficiency, and high power density performance. Packaged
in Vishay’s proprietary 4.5 mm x 3.5 mm MLP package,
SiC530 enables voltage regulator designs to deliver up to
30 A continuous current per phase.
The internal power MOSFETs utilize Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC530 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
and zero current detect to improve light load efficiency. The
driver is also compatible with a wide range of PWM
controllers, supports tri-state PWM, and 5 V PWM logic.
A user selectable diode emulation mode (ZCD_EN#)
function is included to improve the light load performance.
The device also supports the PS4 mode to reduce power
consumption when system operates in standby state.
FEATURES
• Thermally enhanced PowerPAK® MLP4535-22L
package
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 30 A continuous current, 40 A at 10 ms peak
current
• High efficiency performance
• High frequency operation up to 2 MHz
• Power ON reset
• 5 V PWM logic with tri-state and hold-off
• Supports PS4 mode light load requirement for IMVP8 with
low shutdown supply current (5 V, 5 μA)
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
• INTEL IMVP-8 IA / GT core power
• Up to 18 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
5V
PWM
controller
VCIN
ZCD_EN#
PWM
Gate
driver
BOOT
PHASE
VSWH
VIN
VOUT
Fig. 1 - SiC530 Typical Application Diagram
S15-2523-Rev. B, 02-Nov-15
1
Document Number: 62940
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
www.vishay.com
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low-side is turned OFF and the high-side is
turned ON. When PWM input is driven below VPWM_TH_F the
high-side is turned OFF and the low-side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC530 to
pull the PWM input into the tri-state region (see definition of
PWM logic and tri-state, fig. 5). If the PWM input stays in this
region for the tri-state hold-off period, tTSHO, both high-side
and low-side MOSFETs are turned OFF. The function allows
the VR phase to be disabled without negative output voltage
swing caused by inductor ringing and saves a Schottky
diode clamp. The PWM and tri-state regions are separated
by hysteresis to prevent false triggering. The SiC530
incorporates PWM voltage thresholds that are compatible
with 5 V logic.
Diode Emulation Mode and PS4 Mode (ZCD_EN#)
The ZCD_EN# pin enables or disables diode emulation
mode. When ZCD_EN# is driven below VTH_ZCD_EN#_F, diode
emulation is allowed. When ZCD_EN# is driven above
VTH_ZCD_EN#_R, continuous conduction mode is forced.
Diode emulation mode allows for higher converter efficiency
under light load situations. With diode emulation active, the
SiC530 will detect the zero current crossing of the output
inductor and turn off the low-side MOSFET. This ensures
that discontinuous conduction mode (DCM) is achieved.
Diode emulation is asynchronous to the PWM signal,
therefore, the SiC530 will respond to the ZCD_EN# input
immediately after it changes state.
The ZCD_EN# pin can be floated resulting in a high
impedance state. High impedance on the input of ZCD_EN#
combined with a tri-stated PWM output will shut down the
SiC530, reducing current consumption to typically 5 μA.
This is an important feature in achieving the low standby
current requirements required in the PS4 state in ultrabooks
and notebooks.
Voltage Input (VIN)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
SiC530
Vishay Siliconix
Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor.
Ground Connections (CGND and PGND)
PGND (power ground) should be externally connected to
CGND (control signal ground). The layout of the printed circuit
board should be such that the inductance separating CGND
and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V.
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC530 has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning ON from tuning ON until the other
MOSFET’s gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
OFF, before the other can be turned ON. This feature helps
to adjust dead time as gate transitions change with respect
to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC530 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device.
S15-2523-Rev. B, 02-Nov-15
5
Document Number: 62940
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
www.vishay.com
Step 5: Signal Routing
AGND
AGND
Step 7: Ground Connection
SiC530
Vishay Siliconix
AGND
VSWH
PGND
PGND
1. Route the PWM and ZCD_EN# signal traces out of the
top left corner next to pin 1.
2. The PWM signal is an important signal, both signal and
return traces should not cross any power nodes on any
layer.
3. It is best to “shield” these traces from power switching
nodes, e.g. VSWH, with a GND island to improve signal
integrity.
4. GL (pin 19) has been connected with GL pad (pin 24)
internally.
Step 6: Adding Thermal Relief Vias
1. It is recommended to make a single connection between
AGND and PGND which can be made on the top layer.
2. It is recommended to make the entire first inner layer
(below top layer) the ground plane and separate them
into AGND and PGND planes.
3. These ground planes provide shielding between noise
sources on top layer and signal traces on bottom layer.
AGND
VIN
PGND
VSWH
VIN Plane
PGND Plane
1. Thermal relief vias can be added on the VIN and AGND
pads to utilize inner layers for high-current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be placed on VIN plane and PGND plane.
3. VSWH pad is a noise source, it is not recommended to
place vias on this pad.
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal via sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Consult with the
assembly house for guidelines.
S15-2523-Rev. B, 02-Nov-15
11
Document Number: 62940
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet SIC530.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SIC530 | Integrated Power Stage | Vishay |
| SiC531 | Integrated Power Stage | Vishay |
| SiC531A | Integrated Power Stage | Vishay |
| SIC532 | Integrated Power Stage | Vishay |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |