PDF MB85RS64V Data sheet ( Hoja de datos )

Número de pieza	MB85RS64V
Descripción	64K (8K x 8) Bit SPI
Fabricantes	Fujitsu
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No Preview Available ! FUJITSU SEMICONDUCTOR DATA SHEET Memory FRAM DS501-00015-4v0-E 64 K (8 K × 8) Bit SPI MB85RS64V ■ DESCRIPTION MB85RS64V is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS64V adopts the Serial Peripheral Interface (SPI). The MB85RS64V is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS64V can be used for 1012 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS64V does not take long time to write data like Flash memories or E2PROM, and MB85RS64V takes no wait time. ■ FEATURES • Bit configuration : 8,192 words × 8 bits • Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) • Operating frequency : 20 MHz (Max) • High endurance : 1012 times / byte • Data retention : 10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) • Operating power supply voltage : 3.0 V to 5.5 V • Low power consumption : Operating power supply current 1.5 mA (Typ@20 MHz) Standby current 10 μA (Typ) • Operation ambient temperature range : − 40 °C to + 85 °C • Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.9 1 page MB85RS64V ■ SERIAL PERIPHERAL INTERFACE (SPI) MB85RS64V works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK MOSI MISO SPI Microcontroller SS1 SO SI SCK MB85RS64V CS HOLD SO SI SCK MB85RS64V CS HOLD SS2 HOLD1 HOLD2 System Configuration with SPI Port MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select Microcontroller SO SI SCK MB85RS64V CS HOLD System Configuration without SPI Port DS501-00015-4v0-E 5 5 Page MB85RS64V ■ BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. BP1 BP0 Protected Block 0 0 None 0 1 1800H to 1FFFH (upper 1/4) 1 0 1000H to 1FFFH (upper 1/2) 1 1 0000H to 1FFFH (all) ■ WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0XX Protected Protected Protected 10X Protected Unprotected Unprotected 110 Protected Unprotected Protected 111 Protected Unprotected Unprotected ■ HOLD OPERATION Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care. And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the value before transition to HOLD status. CS SCK HOLD Hold Condition Hold Condition DS501-00015-4v0-E 11 11 Page

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