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PDF MB85RQ4ML Data sheet ( Hoja de datos )
| Número de pieza | MB85RQ4ML | |
| Descripción | 4M (512K x 8) Bit Quad SPI | |
| Fabricantes | Fujitsu | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
Memory FRAM
DS501-00043-2v0-E
4 M (512 K × 8) Bit Quad SPI
MB85RQ4ML
■ DESCRIPTION
MB85RQ4ML is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 524,288
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RQ4ML adopts the Quad Serial Peripheral Interface (QSPI) which can realize a high bandwidth such
as Read and Write at 54 MB/s using four bi-directional pins (Quad I/O).
The MB85RQ4ML is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RQ4ML can be used for 1013 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
MB85RQ4ML does not take long time to write data like Flash memories or E2PROM.
MB85RQ4ML is able to write data at a high bandwidth without any waiting time and fits perfectly into
Networking, Gaming, Industrial computing, Camera, RAID controllers, etc.
■ FEATURES
• Bit configuration
: 524,288 words × 8 bits
• Serial Peripheral Interface
: SPI (Serial Peripheral Interface) / Quad SPI
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Write supports
: Single data input / Quad data input / Quad address and data input /
QPI mode
• Read supports
: Single data output / Fast single data output / Fast quad data output /
Fast quad address input and data output / QPI mode / XIP mode
• Operating frequency
: 108 MHz (Except normal READ command)
• High endurance
: 1013 Read/Write per byte
• Data retention
: 10 years (+85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C)
• Operating power supply voltage : 1.7 V to 1.95 V (Single power supply)
• Power consumption
: Operating power supply current 20.0 mA (Typ@Quad I/O 108 MHz)
Standby current 70 μA (Typ), 400 μA (Max)
• Operation ambient temperature range : -40 °C to +85 °C
• Package
: 16-pin plastic SOP (FPT-16P-M24)
RoHS compliant
Copyright 2016 FUJITSU SEMICONDUCTOR LIMITED
2016.10
1 page  
MB85RQ4ML
■ OP-CODE
MB85RQ4ML accepts 8 kinds of SPI Mode command, 4 kinds of Quad SPI Mode command and 2 kinds
of QPI Mode command specified in op-code. Op-code is a code composed of 8 bits shown in the table
below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command
are not performed.
Mode Name
Description
Op-code Max Freq. (MHz) QPI
XIP
WREN Set Write Enable Latch
0000 0110B
108
Yes No
WRDI Reset Write Enable Latch
0000 0100B
108
Yes No
RDSR Read Status Register
0000 0101B
108
Yes No
WRSR Write Status Register
SPI
READ Read
0000 0001B
0000 0011B
108
40
No No
No No
WRITE Write
0000 0010B
108
No No
RDID Read Device ID
1001 1111B
108
No No
FSTRD Fast Read Memory Code
0000 1011B
108
No Yes
FRQO Fast Read Quad Output
0110 1011B
108*
No Yes
Quad FRQAD Fast Read Quad Address and Data 1110 1011B
SPI WQD Write Quad Data
0011 0010B
108*
108
Yes Yes
No No
WQAD Write Quad Address and Data
0001 0010B
108
Yes No
EQPI Enable QPI mode
QPI
DQPI Disable QPI mode
0011 1000B
1111 1111B
108
108
No No
Yes No
*: The frequency when the number of dummy cycles is default value of 6 (see “■ LC MODE”).
Notes
1. “Yes”: Commands are supported in this mode, “No”: Commands are not supported.
2. FRQAD command cannot be issued as 1st command after power-on. Any other command shall be issued
at least once before FRQAD command.
3-1. Single Input Address (3bytes)
SI= X, X, X, X, X, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
(Upper 5bit = any)
3-2. Quad Input Address (3bytes)
IO0=X, A16, A12, A8, A4, A0
IO1=X, A17, A13, A9, A5, A1
IO2=X, A18, A14, A10, A6, A2
IO3=X, X, A15, A11, A7, A3
(Upper 5bit = any)
4-1. Single I/O Data
SI (or SO)=D7, D6, D5, D4, D3, D2, D1, D0
4-2. Quad I/O Data
IO0=D4, D0
IO1=D5, D1
IO2=D6, D2
IO3=D7, D3
DS501-00043-2v0-E
5
5 Page 
MB85RQ4ML
• FSTRD
The FSTRD command reads FRAM memory cell array data. After driving CS low, FSTRD op-code and a
arbitrary 24 address bits are input to SI, followed by 8 mode bits. The 5 upper address bits are ignored.
Then, 8 clock cycles are input to SCK. SO outputs 8 data bits synchronously to the falling edge of SCK.
While reading, the SI value is invalid. When CS is risen, the FSTRD command is completed, otherwise it
keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK
in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting
address, and reading cycle keeps on infinitely. The maximum clock frequency for the FSTRD command is
108 MHz.
Address jumps can be done without the need for additional FSTRD command. This is controlled through
the setting of the Mode bits after the address sequence. This added feature, which is called “XIP mode”,
removes the need for the command sequence. If the Mode bits equal EFH or AFH, then the device remains
in FSTRD mode and the next address can be entered (after CS is raised high and then asserted low) without
requiring the FSTRD command, thus eliminating 8 cycles for the command sequence. If the Mode bits are
any value other than EFH and AFH, then the next time CS is raised high the device will be released from
FSTRD mode. After that, the device can accept SPI commands. CS should not be driven high during mode
bits as this may make the mode bits indeterminate.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 29 30 31 32 33 38 39 40 41 42 43 44 45 46 47
SCK
OP-CODE
24-bit Address
Mode bits
SI 0 0 0 0 1 0 1 1 X X X X X 18 17 16 2 1 0 7 6 1 0 Invalid
MSB
High-Z
LSB MSB LSB MSB Data Out LSB
SO 7 6 5 4 3 2 1 0
Invalid
FSTRD Command Sequence
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 21 22 23 24 25 30 31 32 33 34 35 36 37 38 39
24-bit Address
X X X X X 18 17 16
MSB
High-Z
Mode bits
21076
1 0 Invalid
LSB MSB
LSB MSB Data Out LSB
76543210
Invalid
FSTRD Command Sequence (XIP mode)
DS501-00043-2v0-E
11
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| PDF Descargar | [ Datasheet MB85RQ4ML.PDF ] | |
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