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PDF ST16C654D Data sheet ( Hoja de datos )
| Número de pieza | ST16C654D | |
| Descripción | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO | |
| Fabricantes | Exar | |
| Logotipo |  |
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ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
OCTOBER 2003
REV. 5.0.0
GENERAL DESCRIPTION
The ST16C654/654D1 (654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, transmit and receive FIFO trigger levels,
automatic hardware and software flow control, and
data rates of up to 1.5 Mbps. Each UART has a set of
registers that provide the user with operating status
and control, receiver error indications, and modem
serial interface controls. Selectable interrupt polarity
provides flexibility to meet design requirements. An
internal loopback capability allows onboard
diagnostics. The 654 is available in 64 pin TQFP, 68
pin PLCC and 100 pin QFP packages. The 64 pin
package only offers the 16 mode interface, but the 68
and 100 pin packages offer an additional 68 mode
interface which allows easy integration with Motorola
processors. The ST16C654CQ64 (64 pin) offers
three state interrupt output while the
ST16C654DCQ64 provides continuous interrupt
output. The 100 pin package provides additional
FIFO status outputs (TXRDY# and RXRDY# A-D),
separate infrared transmit data outputs (IRTX A-D)
and channel C external clock input (CHCCLK). The
ST16C654/654D is compatible with the industry
standard ST16C454 and ST16C654/554D.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
• Pin-to-pin compatible with ST16C454, ST16C554
and TI’s TL16C554AFN and TL16C754BFN
• Intel or Motorola Data Bus Interface select
• Four independent UART channels
s Register Set Compatible to 16C550
s Data rates of up to 1.5 Mbps
s 64 Byte Transmit FIFO
s 64 Byte Receive FIFO with error tags
s 4 Selectable TX and RX FIFO Trigger Levels
s Automatic Hardware (RTS/CTS) Flow Control
s Automatic Software (Xon/Xoff) Flow Control
s Progammable Xon/Xoff characters
s Wireless Infrared (IrDA 1.0) Encoder/Decoder
s Full modem interface
• 2.97V to 5.5V supply operation
• Sleep Mode (200 uA typical)
• Crystal oscillator or external clock input
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FIGURE 1. ST16C654 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
CLKSEL
Data Bus
Interface
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc/Buffer
2.97V to 5.5V VCC
GND
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
654 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538• (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
Pin Description
NAME
64-TQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
INTA
(IRQ#)
6
15 12 O When 16/68# pin is at logic 1 for Intel bus interface, this ouput
(OD) becomes channel A interrupt output. 7KH RXWSXW VWDWH LV GHILQHG E\
WKH XVHU DQG WKURXJK WKH VRIWZDUH VHWWLQJ RI 0&5>@ ,17$ LV VHW WR
WKH DFWLYH PRGH ZKHQ 0&5>@ LV VHW WR D ORJLF ,17$ LV VHW WR WKH
WKUHH VWDWH PRGH ZKHQ 0&5>@ LV VHW WR D ORJLF GHIDXOW 6HH
0&5>@
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
INTB
12
21
18 O When 16/68# pin is at logic 1 for Intel bus interface, these ouputs
INTC
37
49
63
INTD
43
55
69
(N.C.)
become the interrupt outputs for channels B, C, and D. 7KH RXWSXW
VWDWH LV GHILQHG E\ WKH XVHU WKURXJK WKH VRIWZDUH VHWWLQJ RI 0&5>@
7KH LQWHUUXSW RXWSXWV DUH VHW WR WKH DFWLYH PRGH ZKHQ 0&5>@ LV VHW
WR D ORJLF DQG DUH VHW WR WKH WKUHH VWDWH PRGH ZKHQ 0&5>@ LV VHW
WR D ORJLF GHIDXOW 6HH 0&5>@
When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.
INTSEL
-
TXRDYA#
TXRDYB#
TXRDYC#
TXRDYD#
-
-
-
-
65 87 I Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-D
pins or override MCR bit-3 and enable the interrupt outputs. Inter-
rupt outputs are enabled continuously by making this pin a logic 1.
Making this pin a logic 0 allows MCR bit-3 to enable and disable the
interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to
enable the continuous output. See MCR bit-3 description for full
detail. This pin must be at logic 0 in the Motorola bus interface
mode. Due to pin limitations on 64 pin packages, this pin is not
available. To cover this limitation, two 64 pin TQFP packages ver-
sions are offered. This pin is bonded to VCC internally in the
ST16C654D so the INT outputs operate in the continuous interrupt
mode. This pin is bonded to GND internally in the ST16C654 and
therefore requires setting MCR bit-3 for enabling the interrupt output
pins.
- 5 O UART channels A-D Transmitter Ready (active low). The outputs
- 25
provide the TX FIFO/THR status for transmit channels A-D. See
- 56
Table 5. If these outputs are unused, leave them unconnected.
- 81
RXRDYA#
RXRDYB#
RXRDYC#
RXRDYD#
-
-
-
-
- 100 O UART channels A-D Receiver Ready (active low). This output pro-
- 31
- 50
vides the RX FIFO/RHR status for receive channels A-D. See
Table 5. If these outputs are unused, leave them unconnected.
- 82
TXRDY#
-
39 45 O Transmitter Ready (active low). This output is a logically ANDed
status of TXRDY# A-D. See Table 5. If this output is unused, leave
it unconnected.
RXRDY#
-
38 44 O Receiver Ready (active low). This output is a logically ANDed status
of RXRDY# A-D. See Table 5. If this output is unused, leave it
unconnected.
5
5 Page 
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
2.4 Channels A-D Internal Registers
Each UART channel in the 654 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the 654 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, FSTAT) that provide automatic RTS and CTS hardware flow control and automatic Xon/Xoff
software flow control. All the register functions are discussed in full detail later in “Section 3.0, UART
INTERNAL REGISTERS” on pag e22.
2.5 INT Ouputs for Channels A-D
The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4
summarize the operating behavior for the transmitter and receiver. Also see Figure 20 through 25.
TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
INT Pin 0 = a byte in THR
1 = THR empty
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
0 = FIFO above trigger level
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO 1 = FIFO below trigger level or FIFO
empty
empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin 0 = no data
1 = 1 byte
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = FIFO below trigger level
1 = FIFO above trigger level
FCR Bit-3 = 1
(DMA Mode Enabled)
0 = FIFO below trigger level
1 = FIFO above trigger level
2.6 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFOs are enabled and the DMA mode
is disabled (FCR bit-3 = 0), the 654 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see Figure 20 through 25.
11
11 Page | ||
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| PDF Descargar | [ Datasheet ST16C654D.PDF ] | |
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