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PDF SP510E Data sheet ( Hoja de datos )

Número de pieza SP510E
Descripción ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
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No Preview Available ! SP510E Hoja de datos, Descripción, Manual

SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FEBRUARY 2014
REV. 1.0.1
GENERAL DESCRIPTION
The SP510E is a highly integrated physical layer
solution that is configurable to support multiple serial
standards. It incorporates eight drivers and eight
receivers (8TX/8RX), configurable for either
differential (V.11 or V.35) or single ended (V.28 and
V.10) signaling.
SP510E enables a Serial Communications Controller
to implement a variety of serial port types including
V.24, V.25, V.36, EIA-530, EIA-530-A, X.21, RS-232.
The device architecture is designed to support the
data and clock signals used in HDLC or SDLC serial
ports as either DTE or DCE.
Operating configuration is programmable in system
using the mode-select pins. The V.11 and V.35 modes
include internal bus termination that may be switched
in or out using the TERM_OFF pin.
The SP510E is ideal for space constrained
applications. It requires only a single 5V supply for full
operation. The VL pin determines the receiver output
voltage (VOH, down to 1.65V), for interfacing with
lower voltage CPUs and FPGAs. For single supply
operation at 5V the VL pin will be connected to VCC.
Fully compliant V.28 and V.10 driver output voltages
are generated using the onboard charge pump.
Special power sequencing is not required during
system startup. Charge pump outputs are internally
regulated to minimize power consumption. The
SP510E requires only four 1µF capacitors for
complete functionality. The device may be put into a
low power shutdown mode when not in active use.
All receivers have fail-safe protection to put outputs
into an output-high state when inputs are open,
shorted, or terminated but idle.
FEATURES
Up to 52Mbps Differential Transmission Rates
±15kV HBM ESD Tolerance for Analog I/O Pins
Integrated Termination Resistors for V.11/V.35
Eight Drivers and Eight Receivers (8TX/8RX)
Adjustable Logic Level Pin VL (Down to 1.65V)
Software Selectable Protocols with 3-Bit Word:
- RS-232 (V.28)
- EIA-530 (V.10 & V.11)
- EIA-530A (V.10 & V.11)
- X.21 (V.11)
- RS-449/V.36
Internal Line or Digital Loopback Testing
Adheres to NET1/NET2 and TBR2 Requirements
Easy Flow-Through Pinout
Single +5V Supply Voltage
Individual Driver/Receiver Enable/Disable Controls
Operates in DTE or DCE Mode
Pin Compatible Upgrade for SP509, SP508
TYPICAL APPLICATIONS
Data Communication Networks
Telecommunication Equipment
Secured Data Communication
CSU and DSU
Data Routers
Network Switches
WAN Access Equipment
VoIP-PBX Gateways
ORDERING INFORMATION
PART NUMBER
SP510EEF-L
SP510ECF-L
PACKAGE
100-pin LQFP
100-pin LQFP
OPERATING TEMPERATURE RANGE
-40°C to +85°C
0°C to +70°C
DEVICE STATUS
Active
Active
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




SP510E pdf
REV. 1.0.1
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
DC ELECTRICAL CHARACTERISTICS
Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V.35 DRIVERS (ALL VALUES MEASURED WITH TERM_OFF = ’0’)
Test Terminated Voltage
VT Figure 26
Offset
VOS Figure 26
Output Overshoot
Figure 26,
VST = Steady State Voltage
Source Impedance
Figure 29
ZS = V2 / V1 x 50
Short Circuit Impedance
Figure 28
±0.44
-0.2VST
50
135
±0.66
±0.6
V
V
+0.2VST V
150
165
V.35 RECEIVERS (ALL VALUES MEASURED WITH TERM_OFF = ’0’)
Sensitivity
Source Impedance
Figure 30
ZS = V2 / V1 x 50
Short-Circuit Impedance
Figure 31
±100 ±200 mV
90 110
135 165
TRANSCEIVER LEAKAGE CURRENT
Driver Output Tri-state Current
Receiver Output Tri-state Current
Drivers disabled, Figure 32
Tx and Rx Disabled,
0.4V VO 2.4V
500
1 10
µA
µA
5

5 Page





SP510E arduino
REV. 1.0.1
FIGURE 1. PIN OUT DIAGRAM
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
VL
GND
SDEN
TTEN
STEN
RSEN
TREN
RRCEN
RLEN
LLEN#
RDEN#
RTEN#
TXCEN#
CSEN#
DMEN#
RRTEN#
ICEN#
TMEN
D0
D1
D2
TERM_OFF
D_LATCH#
NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SP510E
75 TR(a)
74 GND
73 VDD
72 C1P
71 VCC
70 C2P
69 C1N
68 GND
67 C2N
66 VSS1
65 RL(a)
64 VCC
63 LL(a)
62 TM(a)
61 IC
60 RRT(a)
59 RRT(b)
58 GNDV10
57 DM(a)
56 DM(b)
55 CS(a)
54 CS(b)
53 TXC(a)
52 GND
51 TXC(b)
11

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