PDF STK15C88 Data sheet ( Hoja de datos )

Número de pieza	STK15C88
Descripción	256-Kbit (32 K x 8) PowerStore nvSRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! STK15C88 256-Kbit (32 K × 8) PowerStore nvSRAM 256-Kbit (32 K × 8) PowerStore nvSRAM Features ■ 25 ns and 45 ns Access Times ■ Pin compatible with Industry Standard SRAMs ■ Automatic Nonvolatile STORE on power loss ■ Nonvolatile STORE under Software Control ■ Automatic RECALL to SRAM on Power Up ■ Unlimited Read/Write Endurance ■ Unlimited RECALL Cycles ■ 1,000,000 STORE Cycles ■ 100 year Data Retention ■ Single 5 V + 10% Power Supply ■ Commercial and Industrial Temperatures ■ 28-pin (300 mil and 330 mil) SOIC packages ■ RoHS Compliance Logic Block Diagram Functional Description The Cypress STK15C88 is a 256Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap™ technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. PowerStore nvSRAM products depend on the intrinsic system capacitance to maintain system power long enough for an automatic store on power loss. If the power ramp from 5 volts to 3.6 volts is faster than 10 ms, consider our 14C88 or 16C88 for more reliable operation. For a complete list of related documentation, click here. Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-50593 Rev. G • San Jose, CA 95134-1709 • 408-943-2600 Revised March 20, 2015 1 page STK15C88 Hardware Protect The STK15C88 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage conditions. When VCC<VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. Noise Considerations The STK15C88 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise. Low Average Active Power CMOS technology provides the STK15C88 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 2 and Figure 3 show the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5 V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK15C88 depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for accesses 3. The ratio of READs to WRITEs 4. CMOS versus TTL input levels 5. The operating temperature 6. The VCC level 7. I/O loading Figure 2. Current Versus Cycle Time (WRITE) Figure 3. Current Versus Cycle Time (READ) Best Practices nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites, sometimes, reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume a NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration and cold or warm boot status should always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. ■ Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs and incoming inspection routines). Document Number: 001-50593 Rev. G Page 5 of 18 5 Page STK15C88 AutoStore or Power Up RECALL Parameter Alt tHRECALL [10] tSTORE [6] VRESET VSWITCH tRESTORE tHLHZ Switching Waveforms Description Power up RECALL Duration STORE Cycle Duration Low Voltage Reset Level Low Voltage Trigger Level Figure 9. AutoStore/Power Up RECALL STK15C88 Min Max 550 10 3.6 4.0 4.5 VCC 5V VSWITCH VRESET Unit s ms V V AutoStore™ POWER-UP RECALL WE tHRECALL DQ (DATA OUT) tSTORE POWER-UP RECALL BROWN OUT NO STORE DUE TO NO SRAM WRITES NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStore NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStore RECALL WHEN VCC RETURNS ABOVE VSWITCH Note 10. tHRECALL starts from the time VCC rises above VSWITCH. Document Number: 001-50593 Rev. *G Page 11 of 18 11 Page

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