|
|
Número de pieza | CY7C1021DV33 | |
Descripción | 1-Mbit (64 K x 16) Static RAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CY7C1021DV33 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
No Preview Available ! CY7C1021DV33
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
■ Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■ Pin-and function-compatible with CY7C1021CV33
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 60 mA @ 10 ns
■ Low CMOS standby power
❐ ISB2 = 3 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Independent control of upper and lower bits
■ Available in Pb-free 44-pin 400-Mil wide molded SOJ, 44-pin
TSOP II and 48-ball VFBGA packages
Logic Block Diagram
DATA IN DRIVERS
Functional Description
The CY7C1021DV33 is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A15). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A15).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O8 to I/O15. See the truth table
at the end of this data sheet for a complete description of Read
and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a Write operation (CE
LOW, and WE LOW).
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil wide
Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages.
For a complete list of related resources, click here.
A7
A6
A5
A4
64K x 16
A3 RAM Array
A2
A1
A0
COLUMN DECODER
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05460 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 24, 2014
1 page CY7C1021DV33
Capacitance
Parameter [3]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [3]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Test Conditions
Still Air, soldered on a 3 × 4.5
inch, four-layer printed circuit
board
SOJ
59.52
36.75
TSOP II
53.91
21.24
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms [4]
Max Unit
8 pF
8 pF
VFBGA
36
9
Unit
C/W
C/W
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50
1.5 V
(a)
30 pF*
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
(b) Fall Time: 1 V/ns
High-Z characteristics: R 317
3.3 V
OUTPUT
5 pF
R2
351
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 1 (c).
Document Number: 38-05460 Rev. *H
Page 5 of 18
5 Page CY7C1021DV33
Truth Table
CE OE WE BLE BHE
I/O0–I/O7
H X X X X High-Z
L L H L L Data Out
L H Data Out
H L High-Z
L X L L L Data In
L H Data In
H L High-Z
L H H X X High-Z
L X X H H High-Z
I/O8–I/O15
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
Mode
Power-down
Read – All bits
Read – Lower bits only
Read – Upper bits only
Write – All bits
Write – Lower bits only
Write – Upper bits only
Selected, outputs disabled
Selected, outputs disabled
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Document Number: 38-05460 Rev. *H
Page 11 of 18
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet CY7C1021DV33.PDF ] |
Número de pieza | Descripción | Fabricantes |
CY7C1021DV33 | 1-Mbit (64 K x 16) Static RAM | Cypress Semiconductor |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |