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PDF CY7C1339G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1339G | |
| Descripción | 4-Mbit Pipelined Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1339G
4-Mbit (128K × 32) Pipelined Sync SRAM
4-Mbit (128K × 32) Pipelined Sync SRAM
Features
■ Registered inputs and outputs for pipelined operation
■ 128K × 32 common I/O architecture
■ 3.3 V core power supply (VDD)
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 4.0 ns (for 133-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ “ZZ” sleep mode option
Functional Description
The CY7C1339G SRAM integrates 128K × 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:D], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW when active LOW causes all
bytes to be written.
The CY7C1339G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Logic Block Diagram
A0, A1, A
M ODE
ADV
CLK
A DSC
A DSP
BW D
BW C
BW B
BW A
BW E
GW
CE1
CE2
CE3
OE
ZZ
A DDR E SS
REGISTER
2 A [1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD
BYTE
W RITE REGISTER
DQC
BYTE
W RITE REGISTER
DQB
BYTE
W RITE REGISTER
DQA
BYTE
W RITE REGISTER
ENA BLE
REGISTER
PIPELINED
ENA BLE
DQD
BYTE
WRITE DRIVER
DQC
BYTE
WRITE DRIVER
DQB
BYTE
WRITE DRIVER
DQA
BYTE
WRITE DRIVER
M EM ORY
ARRAY
SENSE
AM PS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
INPUT
REGISTERS
SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05520 Rev. *R
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 8, 2016
1 page  
CY7C1339G
Pin Definitions (continued)
Name
I/O
Description
DQs
VDD
VSS
VDDQ
VSSQ
MODE
NC,
NC/9M,
NC/18M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed
in a tri-state condition.
Power supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O power Power supply for the I/O circuitry.
supply
I/O ground Ground for the I/O circuitry.
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
– No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
NC/576M and NC/1G are address expansion pins are not internally connected to the die.
Document Number: 38-05520 Rev. *R
Page 5 of 23
5 Page 
CY7C1339G
Capacitance
Parameter [13]
Description
CIN
CCLK
CI/O
Input capacitance
Clock input capacitance
Input/output capacitance
Thermal Resistance
Parameter [13]
Description
JA
JC
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
100-pin TQFP
Package
5
5
5
Unit
pF
pF
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
30.32
6.85
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
OUTPUT
Z0 = 50
3.3 V
OUTPUT
RL = 50
5 pF
VT = 1.5 V
(a)
INCLUDING
JIG AND
SCOPE
R = 317
R = 351
VDDQ
GND
ALL INPUT PULSES
10%
90%
1 ns
(b) (c)
2.5 V I/O Test Load
OUTPUT
Z0 = 50
2.5 V
OUTPUT
RL = 50
VT = 1.25 V
5 pF
R = 1667
VDDQ
R = 1538
GND
10%
1 ns
ALL INPUT PULSES
90%
INCLUDING
(a)
JIG AND
SCOPE
(b)
(c)
90%
10%
1 ns
90%
10%
1 ns
Note
13. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05520 Rev. *R
Page 11 of 23
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