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PDF CYRF89135 Data sheet ( Hoja de datos )
| Número de pieza | CYRF89135 | |
| Descripción | PRoC - Embedded | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYRF89135
PRoC™ - Embedded
PRoC™ - Embedded
PRoC™ – Embedded Features
■ Single Device, two functions
❐ 8-bit flash based MCU function and 2.4-GHz WirelessUSB™
NL radio transceiver function in a single device
■ RF Attributes
❐ Wide operating range: 1.9 V to 3.6 V
❐ 2.4-GHz WirelessUSB NL Transceiver function
❐ Operates in the 2.4-GHz ISM Band (2.402 GHz–2.479 GHz)
❐ 1-Mbps over-the-air data rate
❐ Receive sensitivity typical: –87 dBm
❐ 1 μA typical current consumption in sleep state
❐ Closed-loop frequency synthesis
❐ Supports frequency-hopping spread spectrum
❐ On-chip packet framer with 64-byte first in first out (FIFO)
data buffer
❐ Built-in auto-retry-acknowledge protocol simplifies usage
❐ Built-in cyclic redundancy check (CRC), forward error
correction (FEC), data whitening
❐ Additional outputs for interrupt request (IRQ) generation
❐ Digital readout of received signal strength indication (RSSI)
■ MCU Attributes
❐ Powerful Harvard-architecture processor
❐ M8C CPU – Up to 4 MIPS with 24 MHz Internal clock, external
crystal resonator or clock signal
❐ Low power at high speed
■ Temperature range: 0 °C to +70 °C
■ Flexible on-chip memory
❐ 32 KB Flash/2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ Partial flash updates
❐ Flexible protection modes
❐ In-system serial programming (ISSP)
■ Precision, programmable clocking
❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ Precision 32 kHz oscillator for optional external crystal
■ Programmable pin configurations
❐ Up to 35 general-purpose I/Os (GPIOs)
❐ Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
❐ 25-mA sink current on each GPIO
• 120 mA total sink current on all GPIOs
❐ Pull-up, high Z, open-drain modes on all GPIOs
❐ CMOS drive mode –5 mA source current on ports 0 and 1
and 1 mA on port 2
❐ 20 mA total source current on port 1.
❐ Configurable input threshold for Port 1.
■ Versatile analog system
❐ Low-dropout voltage regulator for all analog resources
❐ High power supply rejection ratio (PSRR) comparator
❐ 8 to 10-bit incremental analog-to-digital converter (ADC)
■ Additional system resources
❐ I2C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ Emulated E2PROM using flash memory
■ Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Package option
❐ 68-pin 8mm × 8mm × 1.0 mm QFN
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86331 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 3, 2013
1 page  
CYRF89135
SPI
The serial peripheral interconnect (SPI) 3-wire protocol uses
both edges of the clock to enable synchronous communication
without the need for stringent setup and hold requirements.
Figure 1. Basic SPI Configuration
Data is output by
both the Master
and Slave on
one edge of the
Data is registered at the
input of both devices on the
opposite edge of the clock.
clock.
SCLK
MOSI
MISO
A device can be a master or slave. A master outputs clock and
data to the slave device and inputs slave data. A slave device
inputs clock and data from the master device and outputs data
for input to the master. Together, the master and slave are
essentially a circular Shift register, where the master generates
the clocking and initiates data transfers.
A basic data transfer occurs when the master sends eight bits of
data, along with eight clocks. In any transfer, both master and
slave transmit and receive simultaneously. If the master only
sends data, the received data from the slave is ignored. If the
master wishes to receive data from the slave, the master must
send dummy bytes to generate the clocking for the slave to send
data back.
SPI Block
MOSI,
MOSI,
MISO DATA_IN DATA_OUT MISO
SCLK CLK_IN
CLK_OUT SCLK
SYSCLK
INT
SS_
Registers
CONFIGURATION[7:0] CONTROL[7:0]
TRANSMIT[7:0]
RECEIVE[7:0]
I2C Slave
The I2C slave enhanced communications block is a
serial-to-parallel processor, designed to interface the
PRoC-EMB device to a two-wire I2C serial communications bus.
To eliminate the need for excessive CPU intervention and
overhead, the block provides I2C-specific support for status
detection and generation of framing bits. By default, the I2C
Slave Enhanced module is firmware compatible with the
previous generation of I2C slave functionality. However, this
module provides new features that are configurable to
implement significant flexibility for both internal and external
interfacing.
Figure 2. I2C Block Diagram
To/From
GPIO
Pins
SDA_IN
SCL_IN
SDA_OUT
SCL_OUT
I2C_EN
I2C Core
I2C Basic
Configuration
I2C_CFG
I2C_SCR
I2C_DR
HWAddr Cmp
I2C_ADDR
Plus Features
I2C_XCFG
I2C_XSTAT
I2C Plus
Slave
Buffer Module
CPU Port
I2C_BUF
32 Byte RAM
Buffer Ctl
I2C_BP
I2C_CP
MCU_BP
MCU_CP
SYSCLK
STANDBY
The basic I2C features include
■ Slave, transmitter, and receiver operation
■ Byte processing for low CPU overhead
■ Interrupt or polling CPU interface
■ Support for clock rates of up to 400 kHz
■ 7- or 10-bit addressing (through firmware support)
■ SMBus operation (through firmware support)
Enhanced features of the I2C Slave Enhanced Module include:
■ Support for 7-bit hardware address compare
■ Flexible data buffering schemes
■ A ‘no bus stalling’ operating mode
A low power bus monitoring modeThe I2C block controls the data
(SDA) and the clock (SCL) to the external I2C interface through
direct connections to two dedicated GPIO pins. When I2C is
enabled, these GPIO pins are not available for general purpose
use. The enCoRe V LV CPU firmware interacts with the block
through I/O register reads and writes, and firmware
synchronization is implemented through polling and/or
interrupts.
WirelessUSB NL System
WirelessUSB NL, optimized to operate in the 2.4-GHz ISM band,
is Cypress's third generation of 2.4-GHz low-power RF
technology. WirelessUSB NL implements a Gaussian
frequency-shift keying (GFSK) radio using a differentiated
single-mixer, closed-loop modulation design that optimizes
power efficiency and interference immunity. Closed-loop
modulation effectively eliminates the problem of frequency drift,
enabling WirelessUSB NL to transmit up to 255-byte payloads
without repeatedly having to pay power penalties for re-locking
the phase-locked loop (PLL) as in open-loop designs
Among the advantages of WirelessUSB NL are its fast lock times
and channel switching, along with the ability to transmit larger
payloads. Use of longer payload packets, compared to multiple
short payload packets, can reduce overhead, improve overall
power efficiency, and help alleviate spectrum crowding.
Document Number: 001-86331 Rev. **
Page 5 of 41
5 Page 
CYRF89135
Pin Definitions (continued)
This table gives the pin definitions. [1, 2]
Pin No.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
Description
P0[3] Analog I/O, Digital I/O, Integrating input
FIFO FIFO status indicator bit
P0[1] Analog I/O, Digital I/O, Integrating input
VIN Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator.
OCDOE OCD mode direction pin, NC
P2[7] Analog I/O, Digital I/O
P2[5] Analog I/O, Digital I/O, XTAL Out
P2[3] Analog I/O, Digital I/O, XTAL In
P2[1] Analog I/O, Digital I/O
P4[1] Analog I/O, Digital I/O
P3[7] Analog I/O, Digital I/O
SPI_SS Enable input for SPI, active low. Also used to bring device out of sleep state.
P3[5] Analog I/O, Digital I/O
P3[3] Analog I/O, Digital I/O
PKT Transmit/receive packet status indicator bit
P3[1] Analog I/O, Digital I/O
CLK Clock input for SPI interface
MOSI Data input for the SPI bus
MISO Data output (tristate when not active)
P1[7] Digital I/O, Analog I/O, I2C SCL, SPI SS
RST_N RST_N Low: Chip shutdown to conserve power. Register values lost
RST_N High: Turn on chip, registers restored to default value
P1[5] Digital I/O, Analog I/O, I2C SDA, SPI MISO
VDD Core power supply voltage. Connect all VDD pins to VOUT pin.
CCLK OCD CPU CLK OUTPUT, NC
HCLK OCD HIGH SPEED CLK, NC
VIN Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator
P1[3] Digital I/O, Analog I/O, SPI CLK
VOUT 1.8 V output from on-chip LDO. Connect to all Vdd pins, do not connect to external loads.
P1[1] Digital I/O, Analog I/O, TC CLK, I2C SCL, SPI MOSI
GND Ground Pin
VDD Core power supply voltage. Connect all VDD pins to VOUT pin.
XTALO Output of the crystal oscillator gain block
XTALI Input to the crystal oscillator gain block
NC No Connect
TEST1 Reserved for factory test. Do not connect.
P1[0] Analog I/O, Digital I/O, TC DATA, I2C SDA
P1[2] Analog I/O, Digital I/O
P1[4] Analog I/O, Digital I/O, EXT CLK
VDD Core power supply voltage. Connect all VDD pins to VOUT pin.
Document Number: 001-86331 Rev. **
Page 11 of 41
11 Page | ||
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| PDF Descargar | [ Datasheet CYRF89135.PDF ] | |
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