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PDF CYRF69303 Data sheet ( Hoja de datos )
| Número de pieza | CYRF69303 | |
| Descripción | Programmable Radio-on-Chip LPstar | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYRF69303
Programmable Radio-on-Chip LPstar
Programmable Radio-on-Chip LPstar
Features
■ Radio System-on-Chip with built-in 8-bit MCU in a single
device.
■ Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz).
■ On Air compatible with second generation radio
WirelessUSB™ LP and PRoC LP.
■ Pin-to-pin compatible with PRoC LP except the pin 31 and
pin 37.
Intelligent
■ M8C based 8-bit CPU, optimized for human interface devices
(HID) applications
■ 256 bytes of SRAM
■ 8 Kbytes of flash memory with EEPROM emulation
■ In-system reprogrammable through D+/D– pins
■ CPU speed up to 12 MHz
■ 16-bit free running timer
■ Low power wakeup timer
■ 12-bit programmable interval timer with interrupts
■ Watchdog timer
Low Power
■ 21 mA operating current (Transmit at –5 dBm)
■ Sleep current less than 1 A
■ Operating voltage from 2.7 V to 3.6 V DC
■ Fast startup and fast channel changes
■ Supports coin cell operated applications
Reliable & Robust
■ Receive sensitivity typical –90 dBm
■ AutoRate™ - Dynamic Data Rate Reception
❐ Enables data reception for any of the supported bit rates
automatically.
❐ DSSS (250 Kbps), GFSK (1 Mbps)
■ Operating temperature from 0 °C to 70 °C
■ Closed-loop frequency synthesis for minimal frequency drift
Simple Development
■ Auto transaction sequencer (ATS): MCU can remain in sleep
state longer to save power
■ Framing, length, CRC16, and Auto ACK
■ Separate 16 byte transmit and receive FIFOs
■ Receive signal strength indication (RSSI)
■ Built-in serial peripheral interface (SPI) control while in Sleep
Mode
■ Advanced development tools based on Cypress’s PSoC® tools
■ Flexible I/O
■ 2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
■ Each GPIO pin supports high impedance inputs, configurable
pull up, open drain output, CMOS/TTL inputs, and CMOS
output
■ Maskable interrupts on all I/O pins
BOM Savings
■ Low external component count
■ Small footprint 40-pin QFN (6 mm × 6 mm)
■ GPIOs that require no external components
■ Operates off a single crystal
Applications
■ Wireless keyboards and mice
■ Presentation tools
■ Wireless gamepads
■ Remote controls
■ Toys
■ Fitness
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66502 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 18, 2014
1 page  
Pinouts
Figure 1. 40-pin QFN pinout
Corner
tabs
P0.4 1
XTAL 2
VCC 3
P0.3 4
P0.1 5
VBAT1 6
VCC 7
P2.1 8
VBAT2 9
RFBIAS 10
CYRF69303
PRoC LPstar
* E-PAD Bottom Side
30 XOUT / GPIO
29 MISO / GPIO
28 P1.5 / MOSI
27 IRQ / GPIO
26 P1.4 / SCK
25 P1.3 / SS
24 P1.2
23 VDD_Micro
22 P1.1
21 P1.0
CYRF69303
Pin Definitions
Pin Name
Description
1 P0.4 Individually configured GPIO
2 XTAL 12 MHz crystal
3, 7, 16, 40
4
VCC
P0.3
Connected to 2.7 V to 3.6 V supply, through 0.047 F bypass C.
Individually configured GPIO
5 P0.1 Individually configured GPIO
6
Vbat1
Connect to 2.7 V to 3.6 V power supply, through 47 ohm series/1 F shunt C
8 P2.1 GPIO. Port 2 Bit 1
9
Vbat2
Connected to 2.7 V to 3.6 V main power supply, through 0.047 F bypass C
10 RFbias RF pin voltage reference
11 RFp Differential RF to or from antenna
12 GND GND
13 RFn Differential RF to or from antenna
14, 17, 18, 20
NC
15 P2.0 GPIO
19 RESV Reserved. Must connect to GND
21 P1.0 / GPIO 1.0 / ISSP-SCLK
ISSP-SCLK
22 P1.1 / GPIO 1.1 / ISSP-SDATA
ISSP-SDATA
23 VDD_micro MCU supply connected to VCC, max CPU 12 MHz
24 P1.2 GPIO
25 P1.3 / nSS Slave Select
26 P1.4 / SCK SPI Clock
Document Number: 001-66502 Rev. *E
Page 5 of 70
5 Page 
CYRF69303
CPU Architecture
This family of microcontrollers is based on a high-performance,
8-bit, Harvard architecture microprocessor. Five registers control
the primary operation of the CPU core. These registers are
affected by various instructions, but are not directly accessible
through the register space by the user.
Table 3. CPU Registers and Register Name
Register
Flags
Program Counter
Accumulator
Stack Pointer
Index
Register Name
CPU_F
CPU_PC
CPU_A
CPU_SP
CPU_X
The 16-bit Program Counter Register (CPU_PC) allows for direct
addressing of the full eight Kbytes of program memory space.
The Accumulator Register (CPU_A) is the general-purpose
register that holds the results of instructions that specify any of
the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
The Stack Pointer Register (CPU_SP) holds the address of the
current top-of-stack in the data memory space. It is affected by
the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It can also be affected by the
SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] is used to globally enable or disable
interrupts. The user cannot manipulate the Supervisory State
status bit [3]. The flags are affected by arithmetic, logic, and shift
operations. The manner in which each flag is changed is
dependent upon the instruction being executed (for example,
AND, OR, XOR). See Table 20 on page 16.
CPU Registers
Flags Register
The Flags Register can only be set or reset with logical instruction.
Table 4. CPU Flags Register (CPU_F) [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
XIO
Super
Carry
Zero
Global IE
Read/Write
–
–
– R/W R RW RW RW
Default
0
0
0
0
0
0
1
0
Bits 7:5 Reserved
Bit 4
XIO
Set by the user to select between the register banks.
0 = Bank 0
1 = Bank 1
Bit 3
Super
Indicates whether the CPU is executing user code or Supervisor Code (This code cannot be accessed directly by the user).
0 = User Code
1 = Supervisor Code
Bit 2
Carry
Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation.
0 = No Carry
1 = Carry
Bit 1
Zero
Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation.
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0
Global IE
Determines whether all interrupts are enabled or disabled.
0 = Disabled
1 = Enabled
Note This register is readable with explicit address 0xF7. The OR F, expr and AND F, expr must be used to set and clear the CPU_F
bits.
Document Number: 001-66502 Rev. *E
Page 11 of 70
11 Page | ||
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