PDF CYRF6986 Data sheet ( Hoja de datos )

Número de pieza	CYRF6986
Descripción	LPstar 2.4 GHz Radio SoC
Fabricantes	Cypress Semiconductor
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CYRF6986 WirelessUSB™ LPstar 2.4 GHz Radio SoC WirelessUSB™ LPstar 2.4 GHz Radio SoC Features ■ 2.4 GHz direct sequence spread spectrum (DSSS) radio trans- ceiver ■ Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz) ■ On Air compatible with second generation radio WirelessUSB™ LP and PRoC LP ■ Pin-to-pin compatible with WirelessUSB LP except the Pin30 and Pin37 Low Power ■ Operating current: 21 mA (transmit at –5 dBm) ■ Sleep current less than 1 A ■ Operating voltage: 2.7 V to 3.6 V ■ Fast startup and fast channel changes ■ Supports coin-cell operated applications Reliable and Robust ■ Receive Sensitivity typical –90 dBm ■ AutoRate™ – dynamic data rate reception ❐ Enables data reception for any of the supported bit rates automatically. ❐ DSSS (250 Kbps), GFSK (1 Mbps) ■ Operating Temperature: 0 °C to 70 °C ■ Closed-loop frequency synthesis for minimal frequency drift Logic Block Diagram Simple Development ■ Auto transaction sequencer (ATS): Enables MCU to sleep longer ■ Framing, length, CRC16, and auto ACK ■ Separate 16-byte transmit and receive FIFOs ■ Receive signal strength indication (RSSI) ■ Serial peripheral interface (SPI) control while in sleep mode ■ 4 MHz SPI microcontroller interface BOM Savings ■ Low external component count ■ Battery voltage monitoring circuitry ■ Small footprint 40-pin QFN (6 mm × 6 mm) Applications ■ Wireless keyboards and mice ■ Presentation tools ■ Wireless gamepads ■ Remote controls ■ Toys ■ Fitness Applications Support See www.cypress.com for development tools, reference designs, and application notes. IRQ SS SCK MISO MOSI RST Data Interface and Sequencer DSSS Baseband & Framer SPI RSSI Power Management VBAT VDD GFSK Modulator Frequency Synthesizer GFSK Demodulator VCC GND RFP RFN RFBIAS Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-66073 Rev. E • San Jose, CA 95134-1709 • 408-943-2600 Revised January 31, 2017 1 page CYRF6986 ■ Any odd number of bits in error (irrespective of the location). ■ An error burst as wide as the checksum itself. Figure 2 shows an example packet with SOP, CRC16, and lengths fields enabled, and Figure 3 shows a standard ACK packet. Preamble N16us Figure 2. Example Packet Format 2nd Framing Symbol* Preamble SOP1 SOP2 Length <== P a y l o a d ==> 1st Framing Symbol* Packet length 1 Byte Period Figure 3. Example ACK Packet Format Preamble N16us 2nd Framing Symbol Preamble SOP1 SOP2 CRC 16 1st Framing Symbol* C R C Field From Received Packet. 2 Byte Periods Note: 32 us CRC 16 Note: 32 us Packet Buffers All data transmission and reception use the 16 byte packet buffers - one for transmission and one for reception. The transmit buffer allows loading a complete packet of up to 16 bytes of payload data in one burst SPI transaction. This is then transmitted with no further MCU intervention. Similarly, the receive buffer allows receiving an entire packet of payload data up to 16 bytes with no firmware intervention required until the packet reception is complete. The CYRF6986 IC supports packets up to 255 bytes. However, the actual maximum packet length depends on the accuracy of the clock on each end of the link and the data mode. Interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. Auto Transaction Sequencer (ATS) The CYRF6986 IC provides automated support for transmission and reception of acknowledged data packets. When transmitting in transaction mode, the device automatically: ■ Starts the crystal and synthesizer ■ Enters transmit mode ■ Transmits the packet in the transmit buffer ■ Transitions to receive mode and waits for an ACK packet ■ Transitions to the transaction end state when an ACK packet is received or a timeout period expires Similarly, when receiving in transaction mode, the device automatically: ■ Waits in receive mode for a valid packet to be received ■ Transitions to transmit mode, transmits an ACK packet ■ Transitions to the transaction end state (receive mode to await the next packet, and so on.) The contents of the packet buffers are not affected by the transmission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action (as long as packets of 16 bytes or less are used). To transmit data, the MCU must load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware must retrieve the fully received packet in response to an interrupt request indicating reception of a packet. Data Rates The CYRF6986 IC supports the following data rates by combining the PN code lengths and data transmission modes described in the previous sections: ■ 1000 kbps (GFSK) ■ 250 kbps (32 chip 8DR) Functional Block Overview 2.4 GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power, range, and robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to 0 dBm transmit power, with an output power Document Number: 001-66073 Rev. E Page 5 of 23 5 Page CYRF6986 Registers All registers are read and writable, except where noted. Registers may be written to or read from individually or in sequential groups.[1, 2] Table 4. Register Map Summary Address 0x00 0x01 Mnemonic CHANNEL_ADR TX_LENGTH_ADR 0x02 TX_CTRL_ADR 0x03 TX_CFG_ADR 0x04 TX_IRQ_STATUS_ADR 0x05 0x06 RX_CTRL_ADR RX_CFG_ADR 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR[3] CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR 0x1E RX_OVERRIDE_ADR 0x1F 0x26 0x27 0x28 0x29 0x32 0x35 0x39 Register Files 0x20 0x21 0x22 0x23 0x24 0x25 TX_OVERRIDE_ADR XTAL_CFG_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_ADR ANALOG_CTRL_ADR TX_BUFFER_ADR RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR b7 b6 b5 b4 b3 b2 b1 b0 Not Used TX GO Not Used OS IRQ RX GO AGC EN RXOW IRQ RX ACK Channel TX Length TX CLR TXB15 IRQEN TXB8 IRQEN TXB0 IRQEN TXBERR IRQEN TXC IRQEN TXE IRQEN DATA CODE RSVD Data mode Not Used LENGTH PA SETTING RSVD TXB15 IRQ TXB8 IRQ TXB0 IRQ TXBERR IRQ TXC IRQ TXE IRQ RSVD RXB16 IRQEN RXB8 IRQEN RXB1 IRQEN RXBERR IRQEN RXC IRQEN RXE IRQEN LNA FAST ATT HILO TURN EN Not Used RXOW EN VLD EN SOPDET IRQ RXB16 IRQ RXB8 IRQ RXB1 IRQ RXBERR IRQ RXC IRQ RXE IRQ PKT ERR EOP ERR CRC0 Bad CRC RX Code RX Data Mode RX Count RX Length The firmware should set “00010000” to this register while initiating XOUT FN IRQ OD IRQ POL XOUT OP MISO OP ACK EN Not Used SOP EN SOP LEN Not Used Not Used Not Used Not Used SOP Not Used HEN XSIRQ EN MISO OD RSVD FRC END LEN EN Not Used Not Used LNA HINT Not Used XOUT OD IRQ OP Not Used RSVD XOUT IP END STATE Not Used FREQ RSVD SPI 3PIN IRQ GPIO MISO IP RSVD IRQ IP ACK TO SOP TH TH32 TH64 RSSI EOP Not Used RSVD ACK RX ACK TX RSVD RSVD RSVD RSVD RSVD Not Used RSVD RXTX DLY FRC PRE RSVD RSVD RSVD RSVD RSVD CRC SEED LSB CRC SEED MSB CRC LSB CRC MSB CRC LSB CRC MSB STRIM LSB Not Used Not Used STRIM MSB FRC SEN FRC AWAKE Not Used Not Used FRC MAN RXACK RXDR DIS CRC0 DIS RXCRC ACE RSVD MAN TXACK OVRD ACK DIS TXCRC RSVD RSVD RSVD START DLY RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD RSVD RSVD RSVD RXF ABORT EN RSVD RSVD RSVD RSVD AUTO_CAL_TIME AUTO_CAL_OFFSET RSVD RSVD RSVD RSVD RX INV RST Not Used TX INV RSVD RSVD RSVD RSVD ALL SLOW TX Buffer File RX Buffer File SOP Code File Data Code File Preamble File MFG ID File Default[1] -1001000 00000000 00000011 --000101 -------- 00000111 10010-10 -------- -------- 00000000 00000000 10100000 000--100 00000000 0000---- 1-000000 10100101 ----0100 ---01010 0-100000 10100100 00000000 00000000 -------- -------- 11111111 11111111 00000000 ----0000 00000--0 0000000- 00000000 00000000 00000000 00000000 00000000 00000011 00000000 00000000 -------- -------- Note 4 Note 5 Note 6 NA Access[1] -bbbbbbb bbbbbbbb bbbbbbbb --bbbbbb rrrrrrrr bbbbbbbb bbbbb-bb brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb bbb--bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb ----bbbb ---bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb ----bbbb wwwww--w bbbbbbb- bbbbbbbb wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr Notes 1. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined. 2. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode. The GPIOs, and RSSI registers can be accessed in Active Tx and Rx mode. 3. EOP_CTRL_ADR[6:4] must never have the value of “000”, that is, EOP Hint Symbol count must never be “0” 4. SOP_CODE_ADR default = 0x17FF9E213690C782. 5. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F. 6. PREAMBLE_ADR default = 0x333302. Document Number: 001-66073 Rev. E Page 11 of 23 11 Page

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Número de pieza	Descripción	Fabricantes
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