PDF CYRF9935 Data sheet ( Hoja de datos )

Número de pieza	CYRF9935
Descripción	NX 2.4 GHz Low Power Radio
Fabricantes	Cypress Semiconductor
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CYRF9935 WirelessUSB™ NX 2.4 GHz Low Power Radio WirelessUSB™ NX 2.4 GHz Low Power Radio Key Features ■ RF channel – 126 (2400 MHz~2525 MHz) ■ Programmable Data Rate – 2 Mbps/250 Kbps ■ Power Supply Range – 1.9 V to 3.6 V ■ Ultra low power operation ❐ TX Current 12 mA at 0 dBm output power ❐ RX Current 15 mA at 2 Mbps data rate ❐ RX Current 14 mA at 250 Kbps data rate ❐ Idle current 26 µA (Idle-I mode) ❐ Sleep current 900 nA ■ Programmable TX Output Power: ❐ +4 dBm ❐ 0 dBm ❐ –8 dBm ❐ –14 dBm ❐ –20 dBm ■ Sensitivity (0.1%BER): ❐ –93 dBm at 250 kbps ❐ –82 dBm at 2 Mbps ■ Digital RSSI ■ Programmable Payload length – 1 to 32 bytes Block Diagram SPI_nSS SCK MISO MOSI IRQ MODE Baseband TX FIFO SPI Baseband Engine (Framer) RX FIFO ■ Programmable Multi-Level FIFO ❐ 3 Levels of 32 bytes each ❐ 6 Levels of 16 bytes each ■ Automatic Packet Acknowledgement ■ Automatic Packet Resend ■ 8/16 bit hardware CRC ■ Up to 8 Pipes for 1:8 Star Network ■ 4-pin Hardware SPI Interface ■ ±60 ppm 16 MHz crystal ■ Compact 24-pin 4 × 4 mm QFN package Applications ■ Wireless mouse, keyboard, gamepad and presenter ■ Wireless audio and VoRF ■ Remote controller ■ Home automation ■ Wireless sensor network ■ Radio Controlled (R/C) Toy GFSK Modulator Transmitter X PA GFSK Demodulator Receiver X LNA Power Management Frequency Synthesizer ANT1 ANT2 XIN XOUT Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-88748 Rev. F • San Jose, CA 95134-1709 • 408-943-2600 Revised April 11, 2016 1 page CYRF9935 Functional Overview Power on Reset Power on reset is initiated when the voltage on VIN reaches 1.9 V. It takes 50 ms for the power on reset event to complete. After power on reset the radio registers will have default values (refer to Register Sets on page 26) and the radio will be in Idle-I mode. In this mode the radio consumes 26 µA current. External Reset CYRF9935 can also be reset anytime by driving the RST_n pin low for a period greater than 5 µs. The reset signal should be followed by a period of inactivity on the SPI or any other input to the radio for about 1.5 milliseconds. This is required for the crystal oscillator to start-up. External reset is an atomic command (it cannot be interrupted) and will interrupt any other activity on the chip. Interrupt In CYRF9935 the interrupt is provided through the IRQ pin. The interrupt can be configured as active low or active high, by clearing or setting bit 7 of direct register 0x02 respectively. Upon reset, it is configured as active low. There are six interrupt sources in CYRF9935. These interrupts can be enabled or disabled by configuring bits 5:0 of direct register 0x02 (refer to Register Sets on page 26). Table 1 describes the different interrupts that are available. Table 1. Interrupt Sources Interrupt source Description RX_DR TX_DS TX_MAX_ARSC TX_FIFO RX_FIFO RSSI RX data ready TX data sent Maximum retry reached Change in TX FIFO state to the state selected by the TX_FIFO_STA_SEL bits in register 0x28 RX FIFO not empty RSSI refresh done Bit in Register 0x02 for enabling or disabling interrupt 5 4 3 2 1 0 Bit in Register 0x01 (Status) that reflects the state of interrupt 5 4 3 1 0 2 If an interrupt is enabled the IRQ pin reflects the state of the corresponding interrupt source in the register 0x01 (refer to Register Sets on page 26). The IRQ pin remains asserted till the interrupt is cleared. To clear an interrupt set the corresponding bit in status register. RF Pins The CYRF9935 has two RF pins, ANT1 and ANT2, which are used for differential RF input/output. For optimum performance, an LC network (called a matching network) matches WUSB-NX to a conventional 50-ohm antenna. CYRF9935 ANT1 ANT2 Matching network 50 Ohm line Antenna The traces to ANT1 and ANT2 pins are RF traces and should be short and direct. The LC values of the matching network should not be modified from those shown in the Application Circuit on page 33. In addition to matching, they provide attenuation of undesired transmit harmonics. These components should have good high-frequency characteristics, signified by Q factor within the manufacturer datasheets. On the other side of the matching network is an antenna with 50 Ohm impedance. This trace also should be short, if possible. However, in many cases, the antenna needs to be placed in a more optimum position on the PCB, so some additional trace length may be necessary. In such cases, the characteristic impedance of trace should also be 50 Ohm. There should be a solid ground plane on the underside of the matching network. The solid ground plane should extend all the way to the ground pad vias (at the center of the device) on one side and should extend to the 50 Ohm transmission line that connects to the antenna on the other side. RF Channel The RF channel frequency determines the center of the channel used. The channel occupies a bandwidth of less than 1 MHz at 250 kbps and a bandwidth of less than 2 MHz at 2 Mbps. CYRF9935 can operate on frequencies from 2.400 GHz to 2.525 GHz. The programming resolution of the RF channel frequency setting is 1MHz. At 2 Mbps the channel occupies a bandwidth wider than the resolution of the RF channel frequency setting. To ensure non-overlapping channels in 2 Mbps mode, the channel spacing must be 2 MHz or more. At 250 kbps the occupied channel bandwidth is the same or lower than the resolution of the RF channel frequency setting. Document Number: 001-88748 Rev. F Page 5 of 47 5 Page CYRF9935 Address Address field consists of Group Address, Destination Pipe Address and Source Pipe Address. Table 13 shows the construction of Address field. The length of Group Address is programmable from 2 bytes to 4 bytes. Both Destination Pipe Address and Source Pipe Address are one byte in length. Table 13. Address Field Format Group Address 2~4 Bytes Destination Pipe Address 1-Byte Source Pipe Address 1-Byte Table 14. Registers Table for Address control Address (Hex) 0x03 Mnemonic ADDRLNG Bits 6:5 Init 01(B) 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 GROUP_ADDR_0 GROUP_ADDR_1 GROUP_ADDR_2 GROUP_ADDR_3 ADDR_DEV ADDR_P1 ADDR_P2 ADDR_P3 ADDR_P4 ADDR_P5 ADDR_P6 ADDR_P7 ADDR_P8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 0xE7 0xE7 0xE7 0xE7 0xE7 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 When a data packet is sent by TXer, Destination Pipe Address is obtained from ADDR_P1 or ADDR_P2 etc. depending on the pipe number used in the W_TX_PAYLOAD or W_ACK_PAYLOAD commands. Source Pipe Address is obtained from the register ADDR_DEV. Source pipe address in the ACK packet send by the RXer is just a copy of the Destination Pipe Address in the received packet and vice versa. Figure 3 on page 12 shows how to set addresses to work in 8:1 communication. All of TXers and RXer have the same Group Address 0xE1, 0xE2, 0xE3 and 0xE4. RXer can receive the packets coming from TXer1, TXer2…to TXer8. RXer has Device Pipe Address 0x00. Device Pipe Address in both TXer1 and TXer8 are configured with 0x01 and 0x08 respectively. ADDR_P1 on the TXers is set to 0x00 which is the Device Pipe RW Description R/W Group Address length 00: invalid 01: 2 bytes 10: 3 bytes 11: 4 bytes R/W Group Address byte 0 R/W Group Address byte 1 R/W Group Address byte 2 R/W Group Address byte 3 R/W Device PIPE Address R/W PIPE 1 Address R/W PIPE 2 Address R/W PIPE 3 Address R/W PIPE 4 Address R/W PIPE 5 Address R/W PIPE 6 Address R/W PIPE 7 Address R/W PIPE 8 Address Address for the RXer. Similarly the ADDR_P1 to ADDR_P8 on the RXer are set to the Device Pipe Addresses on TXer1 to TXer8 respectively. For example when TXer1 sends the data packet to RXer, Destination Pipe Address is 0x00 from ADDR_P1. TXer1’s Source Pipe Address is 0x01 from ADDR_DEV. When RXer received the data packet from TXer1, it returns ACK packet in which the Source Pipe Address is 0x00 and the destination is the same as the received packet’s Source Pipe Address. The same behaviour is followed when TXer8 wants to send the data packet to RXer. Note: 0xAA and 0x55 are not valid values for GROUP_ADDR_3. These patterns are similar to the patterns used for the preamble and may result in communication failure or high Packet Error Rate. Document Number: 001-88748 Rev. *F Page 11 of 47 11 Page

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