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PDF CYUSB3610 Data sheet ( Hoja de datos )
| Número de pieza | CYUSB3610 | |
| Descripción | SuperSpeed USB to Gigabit Ethernet Bridge Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYUSB3610
EZ-USB GX3: SuperSpeed USB
to Gigabit Ethernet Bridge Controller
EZ-USB GX3: SuperSpeed USB to Gigabit Ethernet Bridge Controller
Features
■ Low-power single chip USB 3.0 to 10/100/1000M Gigabit
Ethernet Bridge Controller with Energy Efficient Ethernet (EEE)
■ Gigabit Ethernet Controller
❐ Supports IEEE 802.3az (Energy Efficient Ethernet)
❐ IEEE 802.3, 802.3u, and 802.3ab compatible
❐ Integrates 10/100/1000Mbps Gigabit Ethernet MAC/PHY
❐ Supports dynamic cable length detection and dynamic power
adjustment Green Ethernet (Gigabit mode only)
❐ Supports parallel detection and automatic polarity correction
❐ Supports crossover detection and auto-correction
❐ Supports IPv4/IPv6 packet Checksum Offload Engine
(COE)
to reduce CPU loading, including IPv4
IP/TCP/UDP/ICMP/IGMP & IPv6 TCP/UDP/ICMPv6
checksum check & generation
❐ Supports TCP Large Send Offload V1
❐ Supports full duplex operation with IEEE 802.3x flow control
and half duplex operation with back-pressure flow control.
❐ Supports IEEE 802.1P Layer 2 Priority Encoding and
Decoding
❐ Supports IEEE 802.1Q VLAN tagging and 2 VLAN ID filtering;
received VLAN Tag (4 bytes) can be stripped off or preserved
❐ Supports Jumbo frame
❐ PHY loop-back diagnostic capability
■ USB Device Controller
❐ Integrates on-chip USB 3.0 PHY and controller
❐ Supports USB 3.0 power saving modes (U0, U1, U2, and U3)
❐ High performance packet transfer rate over USB bus using
burst transfer mechanism
■ Advanced Power Management Features
❐ Supports power management offload (ARP & NS)
❐ Supports dynamic power management to reduce power
dissipation during idle or light traffic
❐ Supports AutoDetach power saving. Soft-disconnect from
USB host when Ethernet cable is unplugged
❐ Supports advanced link down power saving when Ethernet
cable is unplugged
■ Wake-on-LAN Feature
❐ Supports suspend mode and remote wakeup via link-change,
Magic Packet, Microsoft wakeup frame and external wakeup
pin
❐ Supports Bonjour wake-on-demand
■ Supports serial EEPROM (93C56/66) for storing USB
Descriptors, Node-ID, etc
■ Supports automatic loading of USB Device Descriptors,
Node-ID, etc. from internal memory or external EEPROM after
power-on initialization
■ Single 25 MHz clock input from crystal or oscillator source
■ Integrates on-chip power-on reset circuit
■ Integrates pipelined RISC SoC (System on Chip) for handling
protocol and control functions
■ 68-pin QFN 8 mm × 8 mm RoHS/REACH compliant package
■ Operating temperature: 0 °C to 70 °C
Target Applications
■ Docking Station
■ USB Dongle
■ Embedded systems
■ Network Printer
■ USB Port Replicator
■ POS, Card Reader
■ Netbook, UMPC, MID
■ Ultrabook
■ IP STB, IP TV
■ Gaming Console
Functional Description
The GX3 SuperSpeed USB to 10/100/1000M Gigabit Ethernet
Bridge Controller is a high-performance and highly integrated
controller that enables low-cost design, small form-factor, and
simple plug-and-play Gigabit Ethernet network connection
capability for docking stations, desktops, notebook PCs,
Ultrabooks, gaming consoles, digital-home appliances, and any
embedded system using a standard USB port.
GX3 implements a 10/100/1000Mbps Ethernet LAN function
based on IEEE802.3, IEEE802.3u, and IEEE802.3ab standards
with embedded SRAMs for packet buffering. It also integrates an
on-chip 10/100/1000Mbps EEE-compliant Ethernet PHY to
simplify system design. It features a USB interface to
communicate with a USB Host Controller and is compliant with
USB specification v3.0.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-94768 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 3, 2015
1 page  
CYUSB3610
Signal Description
The following abbreviations apply to the following pin description table.
Signal Name
Signal Description
I12 Input, 1.2 V
I3 Input, 3.3 V
I5 Input, 3.3 V with 5 V tolerance
O3 Output, 3.3 V
B5 Bi-directional I/O, 3.3 V with 5 V tolerance
B3 Bi-directional I/O, 3.3 V
P Power/GND
Signal Name
Signal Description
AI Analog Input
AO Analog Output
AB Analog Bi-directional I/O
PU Internal Pull Up (75 kΩ)
PD Internal Pull Down (75 kΩ)
S Schmitt Trigger
T Tri-stateable
Pin Description
Pin Name
Type
Pin No.
Pin Description
USB Interface
DP AB
DM AB
SSTXP
AB
SSTXM
AB
SSRXP
AB
SSRXM
AB
VBUS
I5/PD/S
23 USB 2.0 D+ pin.
24 USB 2.0 D– pin.
29 USB 3.0 SSTX+ pin.
27 USB 3.0 SSTX– pin.
34 USB 3.0 SSRX+ pin.
32 USB 3.0 SSRX– pin.
21 VBUS pin input. Please connect to USB bus power.
Gigabit EEE Ethernet PHY Interface
RSET_BG
AO
47 For Ethernet PHY’s internal biasing. Please connect to GND through a 2.49 kΩ +1% resistor.
MDIP0
MDIN0
AB 53 In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is the transmit
AB
54
pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in
10Base-T and 100Base-TX.
MDIP1
MDIN1
AB 56 In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and is the receive
AB
57
pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in
10Base-T and 100Base-TX.
MDIP2
MDIN2
AB 59 In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair.
AB 60 In MDI crossover mode, this pair acts as the BI_DD+/- pair.
MDIP3
MDIN3
AB 62 In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair.
AB 63 In MDI crossover mode, this pair acts as the BI_DC+/- pair.
Clock Pins
XTALIN
XTALOUT
CLKOUT
CLKIN
I3
O3
O3
I3
38 25 MHz ± 0.005% crystal or oscillator clock input.
39 25 MHz crystal or oscillator clock output.
42 A controllable 25MHz clock output.
Please connect it to CLKIN pin with a 22 Ohm termination resistor near to CLKOUT pin.
50 25 MHz clock input.
Please connect it to CLKOUT pin with a 22 Ohm termination resistor.
Document Number: 001-94768 Rev. *A
Page 5 of 35
5 Page 
CYUSB3610
Default Wake-On-LAN (DWOL) Ready Mode
This Default WOL Ready Mode application is different from normal operation where GX3 Suspend/Resume state usually has to be
configured by software driver during normal system operation. This application applies to a system that uses a predefined remote
wakeup event to turn on the system power supply and its peripheral circuits without having any system software running in the
beginning. This is quite useful when a system has been powered down already and a user needs to power on the system remotely.
GX3 can be configured to support Default WOL Ready Mode, where no system driver is required to configure its WOL related settings
after power on reset. A system design usually partitions its power supply into two or more groups and the GX3 is supplied with an
independent power separated from the system processor. The power supply of GX3 is usually available as soon as power plug is
connected. The power supply of system processor remains off initially when power plug is connected and is controlled by GX3’s PME
pin, which can be activated whenever GX3 detects a pre-defined wakeup event such as valid Magic Packet reception or the WAKEUP#
pin trigger. To reduce power consumption, initially the USB host controller communicating with GX3 can also be unpowered as the
system processor.
The PME pin of GX3 can control the power management IC (PMIC) to power up the system processor along with the USB host
controller, which will perform USB transactions with GX3 after both have been initialized. The pin polarity of PME is configured as
high active when enabling Default WOL Ready Mode. Note that the GX3 must be in self-power (via setting EEPROM Flag [0]) mode
for this function.
Procedure to Enable Default WOL Ready Mode
vcc
GPIO[1]
4.7k
RESET#
WAKEUP#
EN PMIC
PME
GX3
VBUS
DP/DM
Appilcation
Processor
USB
Host
To enable Default WOL Ready Mode, configure GPIO[0] pin as PME (via setting EEPROM Flag [12]) and have GPIO[1] pulled-up
with a 4.7K resistor. After power on reset, GX3 will disable most functions including USB transceiver (see Note 2) but enable Magic
Packet detector logic, internal Ethernet PHY and its auto-negotiation function to be ready to
receive Magic Packet. When a valid Magic Packet is received, GX3 will assert the PME pin to indicate to system processor the wakeup
event. The PME pin, when being configured as static level output signal (via setting EEPROM Flag [15], see Note 3), can be used to
control the power management IC to enable system power supply. After asserting the PME pin, GX3 will also exit from the Default
WOL Ready Mode and revert back to normal operation mode to start normal USB device detection, handshaking, and enumeration.
The PME pin, when being configured as static level output signal, maintains its signal level until RESET# is asserted again. If RESET#
to GX3 is asserted with GPIO[1] pulled-up, the Default WOL Ready Mode will be re-entered. Otherwise (GPIO[1] being pulled-down),
it will enter into normal operation mode and the normal USB device detection, handshaking and enumeration process should take
place right after RESET# negation.
Notes
1. For complete truth table of wakeup events supported, please refer to below on the “GPIO[1] = 1” setting.
2. When the Default WOL Ready Mode is enabled, the DP/DM pins of GX3 will be in tri-state.
3. Please refer to Flag (EEPROM: 05h) on page 15. The bit [15:12] of Flag (PME_IND, PME_TYP, PME_POL, PME_PIN) = 0111.
4. It is recommended that VBUS pin be connected to system power group directly. This way the VBUS will become HIGH when power management IC enables the
system power supply.
Document Number: 001-94768 Rev. *A
Page 11 of 35
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYUSB3610.PDF ] | |
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