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PDF CY7B9945V Data sheet ( Hoja de datos )
| Número de pieza | CY7B9945V | |
| Descripción | High-Speed Multi-Phase PLL Clock Buffer | |
| Fabricantes | Cypress Semiconductor | |
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CY7B9945V RoboClock®
High-Speed Multi-Phase PLL Clock Buffer
High-Speed Multi-Phase PLL Clock Buffer
Features
■ 500 ps max Total Timing Budget (TTB™) window
■ 24 MHz–200 MHz input and Output Operation
■ Low Output-output skew <200 ps
■ 10 + 1 LVTTL outputs driving 50 terminated lines
■ Dedicated feedback output
■ Phase adjustments in 625 ps/1300 ps steps up to +10.4 ns
■ 3.3 V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable
Reference Inputs
■ Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
■ Individual Output Bank Disable
■ Output High Impedance Option for Testing Purposes
■ Integrated Phase Locked Loop (PLL) with Lock Indicator
■ Low Cycle-cycle jitter (<100 ps peak-peak)
■ 3.3 V Operation
■ Industrial Temperature Range: –40 °C to +85 °C
■ 52-pin 1.4 mm TQFP package
Functional Description
The CY7B9945V high-speed multi-phase PLL clock buffer offers
user selectable control over system clock functions. This multiple
output clock driver provides the system integrator with functions
necessary to optimize the timing of high performance computer
and communication systems.
The device features a guaranteed maximum TTB window
specifying all occurrences of output clocks. This includes the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50 while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
enable a divide function of 1 to 12, with phase adjustments in
625 ps–1300 ps increments up to ±10.4 ns. The dedicated
feedback output enables divide-by functionality from 1 to 12 and
limited phase adjustments. However, if needed, any one of the
ten outputs can be connected to the feedback input as well as
driving other inputs.
Selectable reference input is a fault tolerant feature that enables
smooth change over to a secondary clock source when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
For a complete list of related documentation, click here.
Logic Block Diagram
FS
REFA+
REFA-
REFB+
REFB-
REFSEL
FBK
MODE
3
PLL
FBF0
FBDS0
FBDS1
1F0
1F1
1D S 0
1D S 1
1F2
1F3
3
3
3
3
3
3
3
3
3
2F0
2F1
2DS0
2D S 1
3
3
3
3
LO C K
D iv id e
and
Phase
S e le c t
D iv id e
and
Phase
S e le c t
D IS 1
D iv id e
and
Phase
S e le c t
D IS 2
QF
1Q 0
1Q 1
1Q 2
1Q 3
2Q 0
2Q 1
2Q 2
2Q 3
2Q 4
2Q 5
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07336 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 3, 2016
1 page  
CY7B9945V RoboClock®
Block Diagram Description
The PLL adjusts the phase and the frequency of its output signal
to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The CY7B9945V has a flexible REF input scheme. These inputs
enable the use of either differential LVPECL or single ended
LVTTL inputs. To configure as single ended LVTTL inputs, leave
the complementary pin open (internally pulled to 1.5 V), then the
other input pin is used as a LVTTL input. The REF inputs are also
tolerant to hot insertion.
The REF inputs are changed dynamically. When changing from
one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget
(tMIN = tREF (nominal reference period) – tCCJ (cycle-cycle
jitter) – tPDEV (max. period deviation)) while reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the
device. fNOM is directly related to the VCO frequency. The FS
setting for the device is shown in Table 1. For CY7B9945V, the
upper fNOM range extends from 96 MHz to 200 MHz.
Table 1. Frequency Range Select
FS[1]
LOW
MID
HIGH
fNOM (MHz)
Min
24
48
96
Max
52
100
200
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation determines the tU value
as follows:
tU = 1/(fNOM*N).
N is a multiplication factor that is determined by the FS setting.
fNOM is nominal frequency of the device. N is defined in Table 2.
Table 2. N Factor Determination
FS
LOW
MID
HIGH
CY7B9945V
N fNOM (MHz) at which tU = 1.0 ns
32 31.25
16 62.5
8 125
Note
1. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
Document Number: 38-07336 Rev. *M
Page 5 of 18
5 Page 
CY7B9945V RoboClock®
Switching Characteristics
Over the Operating Range [8, 9, 10, 11, 12]
Parameter
Description
fin
fout
tSKEWPR
tSKEWBNK
tSKEW0
tSKEW1
tSKEW2
tCCJ1-3
Clock Input Frequency
Clock Output Frequency
Matched Pair Skew [13, 14], 1Q[0:1], 1Q[2:3], 2Q[0:1],
2Q[2:3], 2Q[4:5]
Intrabank Skew[13, 14]
Output-Output Skew (same frequency and phase,
rise to rise, fall to fall) [13, 14]
Output-Output Skew (same frequency and phase,
other banks at different frequency,
rise to rise, fall to fall) [13, 14]
Output-Output Skew
(all output configurations
outside of tSKEW0 and tSKEW1) [12, 15]
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
tPD
TTB
tPDDELTA
tREFpwh
tREFpwl
Propagation Delay, REF to FB Rise
Total Timing Budget window
(same frequency and phase) [16, 17]
Propagation Delay difference between two devices [18]
REF input (Pulse Width HIGH)[8]
REF input (Pulse Width LOW)[8]
CY7B9945V-2
Min Max
24 200
24 200
– 200
– 250
– 250
– 250
– 500
– 150
– 100
–250
–
–
2.0
2.0
250
500
200
–
–
CY7B9945V-5
Min Max
24 200
24 200
– 200
– 250
– 550
– 650
Unit
MHz
MHz
ps
ps
ps
ps
– 800 ps
–
–
–500
–
–
2.0
2.0
150 ps
Peak-
Peak
100 ps
Peak-
Peak
500 ps
700 ps
200 ps
– ns
– ns
Notes
8. This is for non-three level inputs.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5 V, unless otherwise indicated.
12. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz.
13. Tested initially and after any design or process changes that affect these parameters.
14. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given output frequency.
15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all
outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
16. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affects these parameters.
17. Rise and fall times are measured between 2.0 V and 0.8 V.
18. fNOM must be within the frequency range defined by the same FS state.
Document Number: 38-07336 Rev. *M
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY7B9945V.PDF ] | |
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