PDF CY2DM1502 Data sheet ( Hoja de datos )

Número de pieza	CY2DM1502
Descripción	1:2 CML Fanout Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2DM1502 1:2 CML Fanout Buffer with Selectable Clock Input 1:2 CML Fanout Buffer with Selectable Clock Input Features ■ One current mode logic (CML), High-speed current steering logic (HCSL), or low-voltage positive emitter-coupled logic (LVPECL) input pair distributed to two CML output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) ■ Up to 1.5 GHz operation ■ 8-pin thin shrunk small outline package (TSSOP) package ■ 2.5-V or 3.3-V operating voltage [1] ■ Commercial and industrial operating temperature range Functional Description The CY2DM1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 CML, HCSL, or LVPECL to CML fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz. For a complete list of related documentation, click here. Logic Block Diagram VDD VSS IN IN# VDD Q0 Q0# Q1 Q1# Note 1. Input AC-coupling capacitors are required for voltage-translation applications. Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-56315 Rev. J • San Jose, CA 95134-1709 • 408-943-2600 Revised May 16, 2016 1 page CY2DM1502 DC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter IDD VIH VIL VID[3] VICM IIH IIL VOH VOL CIN Description Operating supply current Input high voltage, CML/HCSL/LVPECL inputs IN and IN# Input low voltage, CML/HCSL/LVPECL inputs IN and IN# Input differential amplitude Input common mode voltage Input high current, CML/HCSL/LVPECL inputs IN and IN# Input low current, CML/HCSL/LVPECL inputs IN and IN# CML output high voltage CML output low voltage Input capacitance Condition All CML outputs floating (internal IDD) See Figure 2 on page 7 See Figure 2 on page 7 Input = VDD[4] Input = VSS[4] Terminated with 50  to VDD[5] Terminated with 50  to VDD[5] Measured at 10 MHz; per pin Min – – –0.3 0.4 0.2 – –150 VDD – 0.1 VDD – 0.7 – Max 50 VDD + 0.3 Unit mA V –V 1.0 VDD – 0.2 150 V V A – A – VDD – 0.3 3 V V pF Thermal Resistance Parameter [6] Description θJA Thermal resistance (junction to ambient) θJC Thermal resistance (junction to case) Test Conditions 8-pin TSSOP Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 162 29 Unit °C/W °C/W Notes 3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV. 4. Positive current flows into the input pin, negative current flows out of the input pin. 5. Refer to Figure 3 on page 7. 6. These parameters are guaranteed by design and are not tested. Document Number: 001-56315 Rev. J Page 5 of 14 5 Page Acronyms Table 1. Acronyms Used in this Document Acronym Description CML current mode logic ESD electrostatic discharge HBM human body model HCSL high-speed current steering logic JEDEC joint electron devices engineering council LVDS low-voltage differential signal LVCMOS low-voltage complementary metal oxide semiconductor LVPECL low-voltage positive emitter-coupled logic RMS root mean square TSSOP thin shrunk small outline package CY2DM1502 Document Conventions Units of Measure Table 2. Units of Measure Symbol Unit of Measure °C degree Celsius dBc decibels relative to the carrier GHz Hz gigahertz hertz k kilohm µA microampere µF microfarad µs microsecond mA milliampere ms millisecond mV millivolt MHz ns megahertz nanosecond  ohm pF picofarad ps picosecond V volt W watt Document Number: 001-56315 Rev. *J Page 11 of 14 11 Page

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Número de pieza	Descripción	Fabricantes
CY2DM1502	1:2 CML Fanout Buffer	Cypress Semiconductor

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