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PDF CY2CP1504 Data sheet ( Hoja de datos )

Número de pieza CY2CP1504
Descripción 1:4 LVCMOS to LVPECL Fanout Buffer
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY2CP1504
1:4 LVCMOS to LVPECL Fanout Buffer
with Selectable Clock Input
1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Features
Select one of two low-voltage complementary metal oxide
semiconductor (LVCMOS) inputs to distribute to four
low-voltage positive emitter-coupled logic (LVPECL) output
pairs
30-ps maximum output-to-output skew
480-ps maximum propagation delay
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 250 MHz operation
Synchronous clock enable function
20-Pin thin shrunk small outline package (TSSOP) package
2.5-V or 3.3-V operating voltage [1]
Commercial and industrial operating temperature range
Functional Description
The CY2CP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2CP1504 can select between
two separate LVCMOS input clocks using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
250 MHz.
For a complete list of related documentation, click here.
Logic Block Diagram
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-56313 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 13, 2016

1 page




CY2CP1504 pdf
CY2CP1504
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
IDD
VIH1
VIL1
VIH2
VIL2
IIH
IIL
VOH
VOL
RP
Description
Operating supply current
Input high voltage, All inputs
Input low voltage, All inputs
Input high voltage, All inputs
Input low voltage, All inputs
Input high current, All inputs
Input low current, All inputs
LVPECL output high voltage
LVPECL output low voltage
Internal pull-up/pull-down
resistance
Condition
All LVPECL outputs floating (internal IDD)
VDD = 3.3 V
VDD = 3.3 V
VDD = 2.5 V
VDD = 2.5 V
Input = VDD[3]
Input = VSS[3]
Terminated with 50 to VDD – 2.0 [4]
Terminated with 50 to VDD – 2.0 [4]
CLK_EN has pull-up only
IN_SEL has pull-down only
Min Max Unit
– 61 mA
2.0
–0.3
VDD + 0.3
0.8
V
V
1.7
–0.3
VDD + 0.3
0.7
V
V
– 150 A
–150
A
VDD – 1.20 VDD – 0.70
VDD – 2.0 VDD – 1.63
60 165
V
V
k
CIN Input capacitance
Measured at 10 MHz; per pin
– 3 pF
Thermal Resistance
Parameter [5]
Description
θJA Thermal resistance
(junction to ambient)
θJC Thermal resistance
(junction to case)
Test Conditions
20-pin TSSOP Unit
Test conditions follow standard test methods and 80 °C/W
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
16 °C/W
Notes
3. Positive current flows into the input pin, negative current flows out of the input pin.
4. Refer to Figure 2 on page 7.
5. These parameters are guaranteed by design and are not tested.
Document Number: 001-56313 Rev. *J
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CY2CP1504 arduino
CY2CP1504
Acronyms
Table 1. Acronyms Used in this Document
Acronym
Description
ESD
electrostatic discharge
HBM
human body model
JEDEC joint electron devices engineering council
LVDS
low-voltage differential signal
LVCMOS low-voltage complementary metal oxide semicon-
ductor
LVPECL low-voltage positive emitter-coupled logic
LVTTL
low-voltage transistor-transistor logic
RMS
root mean square
TSSOP thin shrunk small outline package
Document Conventions
Units of Measure
Table 2. Units of Measure
Symbol
Unit of Measure
°C degree Celsius
dBc decibels relative to the carrier
GHz
Hz
gigahertz
hertz
kkilohm
μA microampere
μF microfarad
μs microsecond
mA milliampere
ms millisecond
mV millivolt
MHz
ns
megahertz
nanosecond
ohm
pF picofarad
ps picosecond
V volt
W watt
Document Number: 001-56313 Rev. *J
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