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PDF CY7B993V Data sheet ( Hoja de datos )
| Número de pieza | CY7B993V | |
| Descripción | High-Speed Multi-Phase PLL Clock Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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RoboClock,,™ CY7B994V
PRELIMINARY
CY7B993V
High-Speed Multi-Phase PLL Clock Buffer
Features
Functional Description
• 12/100-MHz (CY7B993V), or 24/185-MHz (CY7B994V)
output operation
• Matched pair outputs skew <200 ps
• Zero input-to-output delay
• 18 LVTTL 50% duty-cycle outputs capable of driving
50Ω terminated lines
• Commercial Temp. Range with 16 outputs at 185 MHz
• Industrial Temp. Range with 6 outputs at 185 MHz
• 3.3V LVTTL/LV Differential (LVPECL), Fault Tolerant and
Hot Insertable reference inputs
• Phase adjustments in 625/1300 ps steps up to ±10.4 ns
• Multiply/Divide ratios of (1–6, 8, 10, 12):(1–6, 8, 10, 12)
• Operation up to 12x input frequency
• Individual Output Bank disable for aggressive power
management and EMI reduction
• Output high-impedance option for testing purposes
• Fully integrated PLL with Lock Indicator
• Low Cycle-to-Cycle Jitter (<100 ps peak-peak)
• Single 3.3V ± 10% supply
• 100-Pin TQFP package
The CY7B993V and CY7B994V High-Speed Multi-Phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer and communication systems.
Eighteen configurable outputs can each drive terminated
transmission lines with impedances as low as 50Ω while deliv-
ering minimal and specified output skews at LVTTL levels. The out-
puts are arranged in five banks. Banks 1 to 4 of four outputs
allow a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625 ps–1300 ps increments up to 10.4
ns. One of the output banks also includes an independent
clock invert function. The feedback bank consists of two out-
puts, which allows divide-by functionality from 1 to 12 and lim-
ited phase adjustments. Any one of these eighteen outputs
can be connected to the feedback input as well as driving other
inputs.
Selectable reference input is a fault tolerance feature which
allows smooth change over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
Functional Block Diagram
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RoboClock,, is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 8, 2000
1 page  
PRELIMINARY
RoboClock,,™
CY7B993V
CY7B994V
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+ or REFB–) and the FB inputs (FBKA+,
FBKA–, FBKB+ or FBKB–). Correction information is then
generated to control the frequency of the Voltage Controlled
Oscillator (VCO). These two blocks, along with the VCO, form
a Phase-Locked Loop (PLL) that tracks the incoming REF
signal.
nominal output frequency. The equation to be used to deter-
mine the tU value is as follows:
tU = 1/(fNOM*N)
N is a multiplication factor which is determined by the FS set-
ting. fNOM is nominal frequency of the device. N is defined in
Table 2.
Table 2. N Factor Determination
CY7B993V
CY7B994V
The RoboClock,,™ has a flexible REF and FB input scheme.
These inputs allow the use of either differential LVPECL or
single-ended LVTTL inputs. To configure as single-ended
LVTTL inputs, the complementary pin must be left open (inter-
nally pulled to 1.5V), then the other input pin can be used as
a LVTTL input. The REF inputs are also tolerant to hot inser-
tion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the
same frequency, the PLL is optimized to ensure that the clock
outputs period will not be less than the calculated system bud-
get (tMIN = tREF (nominal reference clock period) – tCCJ (cycle-
to-cycle jitter) – tPDEV (max. period deviation)) while re-acquir-
ing lock.
FS
LOW
MID
HIGH
fNOM (MHz) at
fNOM (MHz) at
N which tU =1.0 ns N which tU =1.0 ns
64 15.625 32 31.25
32 31.25 16 62.5
16 62.5 8 125
Divide and Phase Select Matrix
The Divide and Phase Select Matrix is comprised of five inde-
pendent banks: four banks of clock outputs and one bank for
feedback. Each clock output bank has two pairs of low-skew,
high-fanout output buffers ([1:4]Q[A:B][0:1]), two phase func-
tion select inputs ([1:4]F[0:1]), two divider function selects
([1:4]DS[0:1]), and one output disable (DIS[1:4]).
VCO, Control Logic, Divider, and Phase Generator
The VCO accepts analog control inputs from the PLL filter
block. The FS control pin setting determines the nominal op-
erational frequency range of the divide by one output (fNOM) of
the device. fNOM is directly related to the VCO frequency.
There are two versions of the RoboClock,,, a low-speed device
(CY7B993V) where fNOM ranges from 12 MHz to 100 MHz,
and a high-speed device (CY7B994V) which ranges from 24
MHz to 200 MHz. The FS setting for each device is shown in
Table 1.
The feedback bank has one pair of low-skew, high-fanout out-
put buffers (QFA[0:1]). One of these outputs may connect to
the selected feedback input (FBK[A:B]±). This feedback bank
also has one phase function select input (FBF0), two divider
function selects FSDS[0:1], and one output disable (FBDIS).
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for
each bank are shown in Table 4.
Table 3. Output Skew Select Function
The fNOM frequency is seen on “divide-by-one” outputs. For the
CY7B994V, the upper fNOM range extends from 96 MHz to 200
MHz, but the maximum output frequency is limited to185 MHz.
Table 1. Frequency Range Select
Function
Selects
[1:4]F0
and
[1:4]F1 FBF0
Bank1
Output Skew Function
Bank2 Bank3 Bank4
Feed-
back
Bank
FS[2]
LOW
MID
HIGH
CY7B993V
fNOM (MHz)
Min.
Max.
12 26
24 52
48 100
CY7B994V
fNOM (MHz)
Min.
Max.
24 52
48 100
96 200[3]
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
–4tU
–3tu
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
–8tU
–7tU
–6tU
BK1[4]
0tU
BK2[4]
+6tU
+7tU
+8tU
–8tU
–7tU
–6tU
BK1[4]
0tU
BK2[4]
+6tU
+7tU
+8tU
–4tU
NA
NA
NA
0tu
NA
NA
NA
+4tU
Notes:
2. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when
the output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
3. The maximum output frequency is 185 MHz.
4. BK1, BK2 denotes following the skew setting of Bank1 and Bank2 respectively.
5
5 Page 
PRELIMINARY
RoboClock,,™
CY7B993V
CY7B994V
Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] (continued)
Parameter
tOHZ
tOLZ
tOZH
tOZL
Description
DIS[1:4]/FBDIS HIGH to output high-impedance from HIGH[14, 23]
DIS[1:4]/FBDIS HIGH to output high-impedance from LOW[14, 23]
DIS[1:4]/FBDIS LOW to output HIGH from output is high-
impedance[24]
DIS[1:4]/FBDIS LOW to output LOW from high-impedance[24]
CY7B993/4V-5
Min. Max.
1.0 10
1.0 10
0.5[23] 14[25]
CY7B993/4V-7
Min. Max.
1.0 10
1.0 10
0.5[23] 14[25]
0.5[23] 14[25] 0.5[23] 14[25]
Unit
ns
ns
ns
ns
AC Test Loads and Waveform[26]
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Notes:
23. Measured at 0.5V deviation from starting voltage.
24. For tOZL and tOZH minimum, CL = 0pF, RL = 1k (to VCC for tOZL, to GND for tOZH). For tOZL and tOZH maximum, CL= 25pF and RL = 100Ω (to VCC for tOZL, to
GND for tOZH).
25. tOZL maximum is measured at 0.5V. tOZH maximum is measured at 2.4V.
26. These figures are for illustrations only. The actual ATE loads may vary.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7B993V.PDF ] | |
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