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PDF CY8C24393 Data sheet ( Hoja de datos )
| Número de pieza | CY8C24393 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C24X93
PSoC® Programmable System-on-Chip
PSoC® Programmable System-on-Chip
Features
■ Powerful Harvard-architecture processor
❐ M8C CPU with a max speed of 24 MHz
■ Operating Range: 1.71 V to 5.5 V
❐ Standby Mode 1.1 μA (Typ)
❐ Deep Sleep 0.1 μA (Typ)
■ Operating Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ 8 KB flash, 1 KB SRAM
❐ 16 KB flash, 2 KB SRAM
❐ 32 KB flash, 2 KB SRAM
❐ Read while Write with EEPROM emulation
❐ 50,000 flash erase/write cycles
❐ In-system programming simplifies manufacturing process
■ Four Clock Sources
❐ Internal main oscillator (IMO): 6/12/24 MHz
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ External 32 KHz Crystal Oscillator
❐ External Clock Input
■ Programmable pin configurations
❐ Up to 36 general purpose dual mode GPIO (Analog inputs
and Digital I/O supported)
❐ High sink current of 25 mA per GPIO
• Max sink current 120 mA for all GPIOs
❐ Source Current
• 5 mA on ports 0 and 1
• 1 mA on ports 2,3 and 4
❐ Configurable internal pull-up, high-Z and open drain modes
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
■ Versatile Analog functions
❐ Internal Low-Dropout voltage regulator for high power supply
rejection ratio (PSRR)
■ Full-Speed USB
❐ 12 Mbps USB 2.0 compliant
❐ Eight unidirectional endpoints
❐ One bidirectional endpoint
❐ Dedicated 512 byte SRAM
❐ No external crystal required
■ Additional system resources
❐ I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐ Configurable up to 12 MHz SPI master and slave
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ 10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
❐ Two general-purpose Comparators
• 3 Voltage References (0.8 V, 1 V, 1.2 V)
• Any pin to either comparator inputs
• Low-power operation at 10 µA
❐ One 8-bit IDAC with full scale range of 512 µA
❐ One 8-bit Software PWM
■ Development Platform
❐ PSoC Designer™ IDE
■ GPIOs and Package options
❐ 13 GPIOs - QFN 16
❐ 28 GPIOs - QFN 32
❐ 34 GPIOs - QFN 48
❐ 36 GPIOs - QFN 48
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86894 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 24, 2013
1 page  
CY8C24X93
PSoC® Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
■ The Core
■ Analog System
■ System Resources (including a full-speed USB port).
A common, versatile bus allows connection between I/O and the
analog system.
Depending on the PSoC package, up to 36 GPIO are included in
the CY8C24x93 PSoC device. The GPIO provides access to the
MCU and analog mux.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit
Harvard-architecture microprocessor.
Analog system
The analog system is composed of an ADC, two comparators
and an IDAC. It has an internal 0.8 V, 1 V or 1.2 V analog
reference. All the pins can be configured to connect to the analog
system.
ADC
The ADC in the CY8C24x93 device is an incremental
analog-to-digital converter with a range of 8 to 10 bits supporting
signed and unsigned data formats. The input to the ADC can be
from any pin.
IDAC
The IDAC can provide current source up to 512 µA to any GPIO
pin. In the CY8C24x93 family of devices 4 ranges of current
source can be implemented that can vary in 255 steps, and are
connected to analog mux bus.
Table 1. IDAC Ranges
Range
1x
2x
4x
8x
Full Scale Range in µA
64
128
256
512
Comparator
The CY8C24x93 family has two high-speed, low-power
comparators. The comparators have three voltage references,
0.8 V, 1.0 V and 1.2 V. Comparator inputs can be connected from
any pin through the analog mux bus. The comparator output can
be read in firmware for processing or routed out via specific pins
(P1_0 or P1_4).
The output of the two comparators can be combined with 2-input
logic functions. The combinatorial output can be optionally
combined with a latched value and routed to a pin output or to
the interrupt controller. The input multiplexers and the
comparator are controller through the CMP User Module.
Document Number: 001-86894 Rev. *B
Page 5 of 65
5 Page 
CY8C24X93
32-pin QFN (28 GPIOs) [6]
Table 3. Pin Definitions – CY8C24193 [7]
Pin
No.
Type
Digital Analog
Name
Description
1 IOH
I P0[1]
2 I/O
I P2[7]
3 I/O
I P2[5] Crystal output (XOut)
4 I/O
I P2[3] Crystal input (XIn)
5 I/O
I P2[1]
6 I/O
I P3[3]
7 I/O
8 IOHR
9 IOHR
I P3[1]
I P1[7] I2C SCL, SPI SS
I P1[5] I2C SDA, SPI MISO
10 IOHR
11 IOHR
I P1[3] SPI CLK.
I P1[1] ISSP CLK[8], I2C SCL, SPI MOSI.
12 Power
13 IOHR
I
VSS
P1[0]
Ground connection.
ISSP DATA[8], I2C SDA,
SPI CLK[9]
14 IOHR
I P1[2]
15 IOHR
I P1[4] Optional external clock input
(EXTCLK)
16 IOHR
I P1[6]
17
Input
XRES Active high external reset with
internal pull-down
18 I/O
I P3[0]
Figure 2. CY8C24193
AI , P0[1]
AI , P2[7]
AI, XOut, P2[5]
AI , XIn, P2[3]
AI , P2[1]
AI , P3[3]
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
1
2
3
4
5
6
7
8
QFN
(Top View)
24
23
22
21
20
19
18
17
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
19 I/O
I P3[2]
20 I/O
I P2[0]
21 I/O
I P2[2]
22 I/O
I P2[4]
23 I/O
I P2[6]
24 IOH
I P0[0]
25 IOH
I P0[2]
26 IOH
I P0[4]
27 IOH
I P0[6]
28 Power
29 IOH
I
VDD Supply voltage
P0[7]
30 IOH
I P0[5]
31 IOH
I P0[3]
32 Power
CP Power
VSS Ground connection
VSS
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
6. 28 GPIOs.
7.
The center pad (CP) on the QFN
it must be electrically floated and
package must be
not connected to
connected to ground
any other signal.
(VSS)
for
best
mechanical,
thermal,
and
electrical
performance.
If
not
connected
to
ground,
8. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
9. Alternate SPI clock.
Document Number: 001-86894 Rev. *B
Page 11 of 65
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C24393.PDF ] | |
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