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PDF ADGS1412 Data sheet ( Hoja de datos )
| Número de pieza | ADGS1412 | |
| Descripción | Quad SPST Switch | |
| Fabricantes | Analog Devices | |
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Data Sheet
Serially Controlled, 1.5 Ω, On-Resistance,
High Voltage, iCMOS, Quad SPST Switch
ADGS1412
FEATURES
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst and daisy-chain mode
Industry-standard SPI Mode 0 and Mode 3 interface-
compatible
1.5 Ω typical on resistance at 25°C
0.3 Ω typical on-resistance flatness at 25°C
0.1 Ω typical on-resistance match between channels at 25°C
Fully specified at ±15 V, ±5 V, and +12 V
VSS to VDD analog signal range
APPLICATIONS
Automated test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communications systems
Relay replacement
GENERAL DESCRIPTION
The ADGS1412 contains four independent single-pole/single-
throw (SPST) switches. An serial peripheral interface (SPI)
controls the switches. The SPI interface has robust error detection
features such as cyclic redundancy check (CRC) error detection,
invalid read/write address detection, and SCLK count error
detection.
It is possible to daisy-chain multiple ADGS1412 devices together.
Daisy-chain mode enables the configuration of multiple devices
with a minimal amount of digital lines. The ADGS1412 can also
operate in burst mode to decrease the time between SPI
commands.
iCMOS construction ensures ultralow power dissipation, making
the device ideally suited for portable and battery-powered
instruments.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. In the off condition, signal levels up to the supplies
are blocked.
The on-resistance profile is flat over the full analog input range,
which ensures good linearity and low distortion when switching
audio signals.
FUNCTIONAL BLOCK DIAGRAMS
ADGS1412
S1 D1
S2 D2
S3 D3
S4 D4
SPI
INTERFACE
SDO
SCLK SDI CS RESET/VL
Figure 1.
PRODUCT HIGHLIGHTS
1. SPI interface removes the need for parallel conversion,
logic traces and reduces GPIO channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
3. CRC error detection, invalid read/write address detection,
and SCLK count error detection ensures a robust digital
interface.
4. Safety integrity level (SIL)-compatible.
5. Minimum distortion.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADGS1412
Data Sheet
Parameter
POWER REQUIREMENTS
IDD
IL
Inactive
Active at 50 MHz
ISS
VDD/VSS
+25°C −40°C to +85°C −40°C to +125°C Unit
0.001
220
230
µA typ
1 µA max
µA typ
380 µA max
µA typ
380 µA max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
6.3
7
1.8
2
0.7
0.001
8.0
2.1
1.0
1.0
±4.5/±16.5
µA typ
µA max
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/V max
Digital inputs = 0 V or VL
Digital inputs toggle between
0 V and VL, VL = 5.5 V
Digital inputs toggle between
0 V and VL, VL = 2.7 V
Digital inputs = 0 V or VL
GND = 0 V
1 Guaranteed by design; not subject to production test.
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
+25°C −40°C to +85°C −40°C to +125°C Unit
VDD to VSS
V
3.3 Ω typ
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
4 4.9
0.13
0.22 0.23
0.9
1.1 1.24
±0.03
5.4
0.25
1.31
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
Drain Off Leakage, ID (Off )
±0.55 ±2
±0.03
±12.5
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input Voltage
High, VINH
±0.55
±0.05
±1.0
±2
±4
Low, VINL
±12.5
±30
2
1.35
0.8
0.8
nA max
nA typ
nA max
V min
V min
V max
V max
Test Conditions/Comments
VS = ±4.5 V, IS = −10 mA,
see Figure 28
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5 V, IS = −10 mA
VS = ±4.5 V, IS = −10 mA
VDD = +5.5V, VSS = −5.5 V
VS = ±4.5 V, VD = 4.5 V,
see Figure 31
VS = ±4.5 V, VD = 4.5 V,
see Figure 31
VS = VD = ±4.5V, see Figure 27
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
Rev. 0 | Page 4 of 25
5 Page 
ADGS1412
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
D1 1
S1 2
VSS 3
GND 4
S4 5
D4 6
ADGS1412
TOP VIEW
(Not to Scale)
18 D2
17 S2
16 NIC
15 VDD
14 S3
13 D3
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
Figure 5. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic Description
1 D1 Drain Terminal 1. This pin can be an input or output.
2 S1 Source Terminal 1. This pin can be an input or output.
3
4, 11
VSS
GND
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Ground (0 V) Reference.
5 S4 Source Terminal 4. This pin can be an input or output.
6 D4 Drain Terminal 4. This pin can be an input or output.
7, 8, 10, 12, NIC
16, 19, 24
Not Internally Connected.
9 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers
are set to their default.
13 D3 Drain Terminal 3. This pin can be an input or output.
14 S3 Source Terminal 3. This pin can be an input or output.
15 VDD Most Positive Power Supply Potential.
17 S2 Source Terminal 2. This pin can be an input or output.
18 D2 Drain Terminal 2. This pin can be an input or output.
20 SDO Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
21 CS Active Low Control Input. CS is the frame synchronization signal for the input data.
22
SCLK
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
23 SDI Serial Data Input. Data is captured on the positive edge of the serial clock input.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Rev. 0 | Page 10 of 25
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ADGS1412.PDF ] | |
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