PDF CY27410 Data sheet ( Hoja de datos )

Número de pieza	CY27410
Descripción	4-PLL Spread-Spectrum Clock Generator
Fabricantes	Cypress Semiconductor
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CY27410 4-PLL Spread-Spectrum Clock Generator 4-PLL Spread-Spectrum Clock Generator Features ■ Input frequencies ❐ Crystal input: 8 MHz to 48 MHz ❐ Reference clock: 8 MHz to 250 MHz LVCMOS ❐ Reference clock: 8 MHz to 700 MHz differential ■ Output frequencies ❐ 25 MHz to 700 MHz LVDS, LVPECL, HCSL, CML ❐ 3 MHz to 250 MHz LVCMOS ❐ 1 kHz to 8 MHz for one LVCMOS output ■ RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset ■ PCIe 1.0/2.0/3.0 compliant ■ SATA 2.0, USB 2.0/3.0, 1/10-GbE compliant Logic Block Diagram ■ Maximum 12 outputs split in two banks with six outputs each. ❐ Up to eight differential output pairs (HCSL, LVPECL, CML, or LVDS) ❐ Up to 12 LVCMOS outputs ■ Up to 100-ps skew for differential outputs within a bank ■ Four fractional N-type phase-locked loops (PLLs) with ❐ VCXO (±120 ppm with steps of 0.23 ppm) ❐ Spread-spectrum capability (Logic SS and Lexmark profile 0.1% to 5% in 0.1% steps, down or center spread) ■ Supply voltage: 1.8 V, 2.5 V, and 3.3 V ■ Zero-delay buffer (ZDB) and non-zero delay buffer (NZDB) configurations ■ I2C configurable with onboard programming ■ Industrial-grade device, offered in 48-pin QFN (7 × 7 × 1.0 mm) package XIN XOUT IN1P IN1N IN2P IN2N Reference System INI IN1S IN2S INC Output Drivers 1 O1[1..4] PLL1 O2[1..4] PLL2 PLL3 O3[1..4] PLL4 O4[1..4] Output Drivers 2 Register Memory NV Memory PRG Block ADC FS I2C RCAL VIN FS2 FS1 FS0 SCLK SDAT RCCAL BG OSC POR QP LDOs VDD Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-89074 Rev. K • San Jose, CA 95134-1709 • 408-943-2600 Revised July 14, 2016 1 page CY27410 Onboard Programming One can write the device memory on the customer board, enabling the use of a blank device that is not preprogrammed. This enables use of the same device across multiple projects and lets you program the device based on individual projects. Conceptual onboard programming is shown in Figure 7. Figure 7. Onboard Programming POR, Initialize Non Volatile Volatile Control Store Control Registers Device Configuration On Board Programming I2C Functional Features and Application Considerations The CY27410 is a 4-PLL spread-spectrum clock generator targeted at consumer, industrial, and low-end networking applications. The key specifications of the part are differential inputs (2) and outputs (12), supporting frequencies up to 700 MHz. The device has a low RMS phase jitter of 1-ps max and value-added features, such as VCXO, Frequency Select, and PLL Bypass modes. This part is designed to support key standards, such as PCIe 1.0/2.0/3.0, USB 2.0/3.0, and 10GbE. The product supports LVDS, LVPECL, CML, HCSL, and LVCMOS logic levels. Clock Generator The main feature of the CY27410 is frequency generation from an external reference (IN1) or a crystal. There are four variables to determine the final output frequency. They are input REF, the DIV-R (R1), FracN (DIV-N) dividers, and the post dividers (DIV-O). The basic formula for determining the final output frequency is: ■ Clock Generator mode ❐ fOUT = ((REF x DIV-N) / DIV-R) / DIV-O ■ PLL Bypass mode ❐ fOUT = REF / DIV-I or REF / DIV-I / DIV-L The basic PLL block diagram is shown in Figure 8. Each of the outputs from the PLL is fed to the output MUX through a Delay circuit that provides a certain delay to the individual clock, if needed. Figure 8. PLL Block Diagram, Clock Generation Reference R1 R2 Synthesis Block PLL FracN C1 O1 DLY O2 O3 O4 Outputs I1 I2 L1 from Adjacent PLL PCIE (HCSL) Clock Generation For PCIe applications, the CY27410 provides eight differential outputs that have the same spread on it at any particular point of time. VCXO and Related Frequencies The CY27410 provides VCXO functionality and a cascading PLL option to generate critical frequencies with a fixed reference. Digital televisions have a requirement for the audio and video clocks to follow a 27-MHz VCXO signal so that they are synchronized. The architecture of the chip must ensure that this is met by cascading, as shown in Figure 9. Figure 9. Cascading PLLs REF XBUF SS_PLL 100MHz HCSL 66.66MHz LVCMOS VIN VCFS (PLL1) 27MHz VCXO FS PLL VIDEO 74.25MHz FS PLL AUDIO 36.864MHz Apart from having the audio and video clocks following the 27-MHz VCXO input, they also need complex divider ratios to generate the output frequencies. Commonly used divider ratios for audio and video signals are listed in Table 1. Table 1. Audio and Video Frequencies Output Frequency 74.17582418 33.8688 22.5792 16.9344 11.2896 5.6448 36.864 Ratios 91:250 625:784 1875:1568 1250:784 1875:784 1875:392 375:512 Document Number: 001-89074 Rev. K Page 5 of 29 5 Page CY27410 Table 3. CY27410 Pin Definitions (continued) Name I/O Type # of Pins OUT24P O LVCMOS / Differential 1 OUT24N O Differential 1 OUT25 OUT26 DNU SDAT SCLK FS0 FS1 FS2 VIN VDDIO_D1 VDDIO_S1 VDDIO_D2 VDDIO_S2 VDD O LVCMOS O LVCMOS I/O I I I I I PWR PWR PWR PWR PWR LVCMOS / Open Drain LVCMOS LVCMOS LVCMOS LVCMOS Analog PWR PWR PWR PWR PWR 1 1 1 1 1 1 1 1 1 1 1 1 1 9 XRES GND VCCD I GND Analog LVCMOS GND Analog 1 E-PAD 1 Pin # 20 21 22 24 10 33 Function Output 24 true output (differential) or Output 24 LVCMOS output Output 24 complement output (differential) connect to OUT24P for LVCMOS LVCMOS clock output 25 LVCMOS clock output 26 Pin for test purpose I2C serial data pin 34 30 31 32 26 44 38 17 23 1, 2, 7, 11, 12, 25, 29, 35, 36 27 28 I2C clock pin Frequency Select pin Frequency Select pin Frequency Select pin Voltage input for ADC Output power supply for Bank 1 differential outputs Output power supply for Bank 1 LVCMOS outputs Output power supply for Bank 2 Differential outputs Output power supply for Bank 2 LVCMOS outputs Core power supply Active low RESET SIGNAL Supply ground For 1.8-V operation, connect to VDD. For 2.5-V or 3.3-V operation, do not connect to VDD; connect a 100-nF capacitor between this pin and GND. Document Number: 001-89074 Rev. *K Page 11 of 29 11 Page

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