PDF CY24292 Data sheet ( Hoja de datos )

Número de pieza	CY24292
Descripción	Four Outputs PCI-Express Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY24292 Four Outputs PCI-Express Clock Generator Four Outputs PCI-Express Clock Generator Features ■ 25 MHz Crystal or Clock Input ■ Four Differential 100 MHz PCI-Express Clocks ■ Supports HCSL Compatible Output Levels ■ One Single-ended 25 MHz Output ■ Spread Spectrum Capability on all 100 MHz PCI-Express Clock Outputs ■ SMBus Interface with Read Back Capability ■ 32-pin QFN Package ■ Operating Voltage 3.3 V ■ Commercial and Industrial Operating Temperature Range Functional Description CY24292 is a clock generator device intended for PCI-Express applications. The device includes: four 100 MHz differential clocks with HCSL Compatible outputs for PCI-Express, and one single-ended 25 MHz output. Using a serially programmable SMBus interface, the CY24292 incorporates spread spectrum modulation on all four 100 MHz outputs. The device incorporates a Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction. The spread feature or individual outputs can also be disabled using the SMBus interface. For a complete list of related documentation, click here. Logic Block Diagram VDD XIN/EXCLKIN (25 MHz) XOUT SCLK SDATA PD_RESET# Clock Buffer/ Crystal Oscillator PLL Clock Synthesizer, Dividers, Buffers and Configuration Logic PCIE0P (100 MHz) PCIE0N PCIE1P (100 MHz) PCIE1N PCIE2P (100 MHz) PCIE2N PCIE3P (100 MHz) PCIE3N 25M (25 MHz) GND I REF R = 475 Ohms 1% REF Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-46142 Rev. E • San Jose, CA 95134-1709 • 408-943-2600 Revised December 5, 2014 1 page CY24292 Table 2. Block Read and Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Block Write Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command code – 8-bit ‘00000000’ stands for block operation Acknowledge from slave Byte count – 8 bits Acknowledge from slave Data byte 0 – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte N/Slave acknowledge Data byte N – 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 Block Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command code – 8-bit ‘00000000’ stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data bytes from slave/acknowledge Data byte N from slave – 8 bits Not acknowledge Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 10 11:18 Write = 0 Acknowledge from slave Command code – 8 bits ‘1xxxxxxx’ stands for byte operation, bits[6:0] of bits[6:0] the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 20:27 Data byte from master – 8 bits 28 Acknowledge from slave 29 Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Byte Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command code – 8 bits ‘1xxxxxxx’ stands for byte operation, of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits Not acknowledge Stop Document Number: 001-46142 Rev. E Page 5 of 19 5 Page CY24292 DC Electrical Characteristics Unless otherwise stated, VDD = 3.3V ±0.3V, ambient temperature = -40°C to 85°C Industrial, 0°C to 70°C Commercial, RREF = 475 Parameter[2] Description Condition Min Typ Max Unit VOL1 VOH1 VOL2 VOH2 VOL3 IOH VIL1 VIH1 VIL2 Low level output voltage of 25M clock IOL = 8 mA High level output voltage of 25M clock IOH = –8 mA Low level output voltage of 100M clocks HCSL termination (RS = 33 , RT = 49.9 ) High level output voltage of 100M clocks HCSL termination (RS = 33 RT49.9 Low level output voltage SDATA IOL = 4mA Output high current for differential clocks IOH = 6IREF Low level input voltage of SCLK, SDATA High level input voltage of SCLK, SDATA Low level input voltage of XIN/EXCLKIN, PD_RESET# pins – – 0.4 V VDD – 0.4 -0.2 – 0 – 0.05 V V 0.65 0.71 0.95 V – – 0.4 V -13 -15.2 -17 mA -0.3 – 0.8 V 2.1 – VDD+0.3 V -0.3 – 0.8 V VIH2 High level input voltage of XIN/EXCLKIN, PD_RESET# pins 2.0 – VDD+0.3 V IDD Operating supply current No load, PD_RESET# pin = 1 Full load, PD_RESET# pin = 1 – 50 70 mA – 135 170 mA IDDPD CIN RPU RPD Power down current Input capacitance Pull up resistor, PD_RESET# Pull down resistor, 25M output PD_RESET# pin = 0 All input pins PD_RESET# = 0 – 250 350 A – 5 – pF – 90 – k 50 – 150 k Note 2. Parameters are guaranteed by design and characterization. Not 100% tested in production. Document Number: 001-46142 Rev. E Page 11 of 19 11 Page

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