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PDF NJW4113-T1 Data sheet ( Hoja de datos )
| Número de pieza | NJW4113-T1 | |
| Descripción | LDO | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJW4113-T1
Io=500mA LDO with Watchdog Timer
GENERAL DESCRIPTION
The NJW4113 is a 500mA output low dropout voltage regulator
with watchdog timer(WDT).
It has a detecting circuit to monitor output voltage and a watchdog
timer function for clock monitor. Detecting voltage is adjustable with
external resistor.
Low consumption current characteristic contributes to reduce
burden on automotive battery in full-time operating application.
Because of operating wide temperature range from -40°C to
+125°C, the NJW4113 suits for high reliability application such as
automotive application.
■ PACKAGE OUTLINE
NJW4113GM1
FEATURES
Wide Operating Voltage Range
4.0V to 40V max.
Low Current Consumption
37μA typ.
High Precision Output Voltage
Vo 1.0%(Ta=25 C)
Vo 1.5%(Ta=-40 C to 125 C)
High Precision Detection Voltage
Output Current
VDET 1.0%(Ta=25 C)
VDET 2.0%( Ta=-40 C to 125 C)
Io(min.)=500mA
Adjustable Detection Voltage with external resistor
Setting WDT Monitor Time, WDT Reset Time and Output Delay Hold Time with external capacitor
Watchdog Timer Enable Function
Correspond to Low ESR capacitor (MLCC)
Thermal shutdown circuit
Over Current Protection
Package Outline
HSOP8
PIN CONFIGURATION
CLK
RSADJ
1.
VRO 2.
WDEN 3.
CW GND 4.
VIN VOUT 5.
6.
Exposed PAD on backside
7.
connected to GND
8.
CLK
RSADJ
CW
VIN
VOUT
GND
WDEN
VRO
Clock Input Pin
External Resistor Pin for Adjusting Detection Voltage
External Capacitor Pin for Setting WDT Monitor Time/ Output delay hold Time
Input Voltage Pin
Output Voltage Pin
Ground Pin
Watchdog Timer Disenable Pin
Reset Output Pin
■ PRODUCT CLASSFICATION
Status
M.P.
PLAN
Device Name
NJW4113GM1-A46-T1
NJW4113GM1-A41-T1
NJW4113GM1-B03-T1
Version
A
B
Output
Voltage
5.0V
3.3V
Detection
Voltage
4.6V
4.1V
3.0V
Ver.2015-07-16
-1-
1 page  
NJW4113-T1
ELECTRICAL CHARACTERISTICS
(Watchdog Timer Block)
(Unless otherwise noted, VIN= VO +1V, CIN=1.0μF, CO=4.7μF, Ta=25 C)
PARAMETER
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
Clock input High-level
Clock input Low-level
Clock Input Pulse Width
Clock Input Cycle
CW Pin Discharge Current
CW Pin Charge Current
High-side
Threshold Voltage
Low-side
Threshold Voltage
WDT Monitor Time
WDT Reset Time
-----------------------
WDEN Pin Threshold
Voltage at WDT Disable
-----------------------
WDEN Pin Threshold
Voltage at WDT Enable
VTCKH
VTCKL
tCKW
tCK
ICW
ICWL
VTCWH
VTCWL
tWD
tWR
VTWDIS
VTWEN
A version
A version, Ta= -40ºC to +125ºC
B version
B version, Ta= -40ºC to +125ºC
A version
A version, Ta= -40ºC to +125ºC
B version
B version, Ta= -40ºC to +125ºC
Ta= -40ºC to +125ºC
Ta= -40ºC to +125ºC
VCW = 0.5V
VCW = 0.5V, Ta= -40ºC to +125ºC
VCW = 0.5V
VCW = 0.5V, Ta= -40ºC to +125ºC
Ta= -40ºC to +125ºC
Ta= -40ºC to +125ºC
CW=0.01μF
CW=0.01μF, Ta= -40ºC to +125ºC
CW=0.01μF
CW=0.01μF, Ta= -40ºC to +125ºC
Ta= -40ºC to +125ºC
Ta= -40ºC to +125ºC
4.0 -
-
4.0 -
-
2.6 -
-
2.6 -
-
- - 1.0
- - 1.0
- - 0.7
- - 0.7
0.05 -
-
0.05 -
-
0.1 -
-
0.1 -
-
1.5 2
2.5
1.1 -
2.9
36
9
3-
9
0.97 1.00 1.03
0.95 -
1.05
0.18 0.2 0.22
0.16 -
0.24
2.9 4.0
5.8
2.5 -
7.9
0.6 1.3
2.9
0.3 -
3.2
1.6 -
-
1.6 -
-
- - 0.3
- - 0.3
V
V
ms
ms
µA
µA
V
V
ms
ms
V
V
The above specification is a common specification for all output voltages.
Therefore, it may be different from the individual specification for a specific output voltage.
* These parameters are tested by Pulse Measurement.
Ver.2015-07-16
-5-
5 Page 
Application Manual
NJW4113-T1
Watchdog timer (WDT) Monitor Time, Watchdog timer (WDT) Reset Time
The NJW4113 can be set the WDT Monitor time tWD for the monitoring the clock(CLK) of a microcomputer.
If it does not detect a CLK rising edge within tWD, then VRO pin outputs "L" level.
VRO keeps "L", for the period which is set by the WDT Reset Time tWR.
(4) Standby state of CLK rising edge detection.
CLK rising edge will be detectable after CW is discharged by ICW and VCW is equal or less than the High-side
Threshold Voltage VTCWH(typ.1.0V).
(5) When detect a CLK rising edge
When detects a CLK rising edge, CW is switched from discharge cycle by ICW to charge cycle by ICWL (typ. 6μA)
and VCW rises. Then, VCW reaches to VTCWH , Cw is switched to discharge cycle and returns to state of the “(4)
Standby state of CLK rising edge detection”.
(6) When don’t detect CLK rising edge
When VCW reaches to the Low-side threshold Voltage VTCWL(typ.0.2V) without detecting CLK rising edge while
CW discharge cycle, VRO is switched from “H” to “L” and Cw is switched to charge cycle.
The WDT Monitor Time tWD is the period wherein VCW falls from VTCWH to VTCWL without detecting CLK rising
edge.
(7) Start of WDT Reset Time
VRO is kept ”L” while CW is charged by ICWL till VCW reaches VTCWH. When VCW beyond VTCWH, VRO is switched
from “L” to “H”. Then returns to the watchdog timer monitor period as start to discharge capacitor CW by ICW.
The period which keeps VRO =”L” is taken as WDT Reset Time tWR.
Detection of Output Voltage drop
(8) When it becomes VOUT VDET.
When VOUT becomes less than VDET while tWD or tWR, VRO is switched to “L” and VCW is 0V due to CW is rapidly
discharged. Then operation returns to the “(1) Initialized state”.
Disable to WDT monitor function
――――――
(9) When Watchdog Timer Disenable pin WDEN=“H”.
――――――
The NJW4113 disables the WDT function by setting WDEN=“H”.
At this time, VCW is fixed at 2V after CW is charged to the IC’s internal power supply (VREG=2V). And if state of
VOUT VDET, VRO keeps ”H”.
When setting W――D――E―N―=“L” or “Open”, CW is discharged. After VCW becomes less than VTCWH, then WDT
function is restarted.
――――――
If set WDEN=“H” during the period of tWR, WDT function stops after the tWRperiod passes.
At the time of an Input Voltage VIN drops
(10) When the output voltage VOUT drops to 0V.
VRO keeps ”L” till the output voltage VOUT becomes around 0.8V.
Ver.2015-07-16
- 11 -
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet NJW4113-T1.PDF ] | |
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