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PDF NJU26126 Data sheet ( Hoja de datos )
| Número de pieza | NJU26126 | |
| Descripción | Digital Signal Processor | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJU26126 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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NJU26126
Digital Signal Processor
■ General Description
The NJU26126 is a high performance 24-bit digital signal processor.
The NJU26126 provides L/R channel independent 10bands PEQ, Low/High
bandwidth independent DRC of FIR filter adoption, Tone Control, Lip sync Audio
Delay, eala & eala Rebirth of NJRC Original Sound Enhancement, Dynamic
Bass Boost, two systems Limiter, and 5.1 channel output function. These kinds
of sound functions are suitable for TV, mini-component, CD radio-cassette,
Sound bar and speakers system.
■Package
NJU26126VC2
■ FEATURES
- Software
• NJRC Original Sound Enhancement (eala, eala Rebirth, Dynamic Bass Boost)
• HPF, LPF, Center/Sub woofer and Surround output function
• 10bands PEQ (Parametrical Equalizer) : L/R channel independent operation
• DRC (Dynamic Range Compression) : 2-bands independent operation (FIR filter adoption)
• Tone Control (Bass / Treble)
• Limiter (SDO0 / SDO1)
• Lip sync Audio Delay (fs=48kHz : Max. 22msec)
• Signal level detector
• Watchdog Clock Output
- Hardware
• 24bit Fixed-point Digital Signal Processing
• Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
• Digital Audio Interface
: 3 Input ports / 3 Output ports
• Digital Audio Format
: I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs
• Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
• Host Interface
: I2C bus (Fast-mode/400kbps)
• Power Supply
: 3.3V
• Input terminal
: 5V Input tolerant
• Package
: SSOP24-C2 (Pb-Free)
Ver.2010-08-19
-1-
1 page  
NJU26126
■ Electric Characteristics
Table 3 Electric Characteristics
Parameter
Symbol
Test Condition
Operating Voltage *1
Operating Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage *3
Low Level Output Voltage
Leakage Current *4
Clock Frequency
Clock Jitter *5
Clock Duty Cycle
VDD
IDD
VIH
VIL
VOH
VOL
IIN
IIN(PU)
IIN(PD)
fOSC
fJIT(CC)
rEC
VDD pin
At no load
(IOH= -1mA)
(IOL= 1mA)
VIN = VSS to VDD
CLK, MCK *6
( VDD=3.3V, fOSC=12.288MHz, Ta=25°C )
Min.
Typ.
Max.
Units
3.0 3.3 3.6 V
- 20 35 mA
VDD x 0.7 - VDD *2
0
VDD x 0.8
-
-
VDDx 0.3
VDD
V
0 - VDDx 0.2
-10 -
10
-120 -
10 µA
-10 - 120
10 12.288 13 MHz
0 - ±3.0 ns
45 50 55 %
*1 VDD of The NJU26126 should be within electric characteristics. When turn on VDD, the voltage should be
increase monotonously. After rise up the voltage to within electric characteristics, the voltage should be not under
electric characteristics. When re-start the NJU26126 after cut the power, the voltage of VDD should be drop to
GND level.
*2 Input pin, Output pin and Open-Drain input/output pin are +5.0V tolerant except CLK input pin.
*3 Except No.18pin: WDC (Open-Drain output) and No.22: SDA (Open-Drain input/output).
*4 I IN(PU) : 18pin, I IN(PD) : 15, 16, 17, 24 pin
*5 Clock Jitter shows Cycle-to-cycle period jitter (JEDEC JESD65).
*6 Provide clock frequency for fOSC spec. NJU26126 needs clock frequency 12.288MHz when sampling rate is 48kHz.
Ver.2010-08-19
-5-
5 Page 
NJU26126
The NJU26126 can use three kinds of formats hereafter as industry-standard digital audio data format; (1)
I2S (2) Left-Justified (3) Right-justified and 16 / 18 / 20 / 24bits data length. (Fig.6-1 to Fig6-12)
An audio interface input and output data format become the same data format.
LRI, LRO
BCKI, BCKO
SDI, SDO
Left Channel
Right Channel
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig.6-1 I2S Data Format 64fs, 24bit Data
LRI, LRO
BCKI, BCKO
SDI, SDO
Left Channel
Right Channel
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
Fig.6-2 Left-Justified Data Format 64fs, 24bit Data
23
LRI, LRO
BCKI, BCKO
SDI, SDO 2 1 0
Left Channel
Right Channel
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
Fig.6-3 Right-Justified Data Format 64fs, 24bit Data
LRI, LRO
BCKI, BCKO
SDI, SDO
Left Channel
Right Channel
MSB LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig.6-4 I2S Data Format 64fs, 20bit Data
LRI, LRO
BCKI, BCKO
SDI, SDO
Left Channel
MSB LSB
1918 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32Clocks
Right Channel
MSB LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32Clocks
Fig.6-5 Left-Justified Data Format 64fs, 20bit Data
19
LRI, LRO
BCKI, BCKO
SDI, SDO 2 1 0
Left Channel
Right Channel
MSB LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
MSB LSB
19 18 17 16 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
32Clocks
Fig.6-6 Right-Justified Data Format 64fs, 20bit Data
Ver.2010-08-19
- 11 -
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NJU26126.PDF ] | |
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