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PDF ADUM4136 Data sheet ( Hoja de datos )
| Número de pieza | ADUM4136 | |
| Descripción | IGBT Gate Driver | |
| Fabricantes | Analog Devices | |
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Data Sheet
Single-/Dual-Supply, High Voltage Isolated
IGBT Gate Driver
ADuM4136
FEATURES
4 A peak drive output capability
Output power device resistance: <1 Ω
Desaturation protection
Isolated fault output
Soft shutdown on fault
Isolated fault and ready functions
Low propagation delay: 55 ns typical
Minimum pulse width: 50 ns
Operating temperature range: −40°C to +125°C
Output voltage range to 35 V
Input voltage range from 2.5 V to 6 V
Output and input undervoltage lockout (UVLO)
Creepage distance: 7.8 mm minimum
100 kV/μs minimum common-mode transient immunity (CMTI)
20-year lifetime for 600 V rms or 1092 V dc working voltage
Safety and regulatory approvals (pending)
5 kV ac for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak (basic)
APPLICATIONS
MOSFET/IGBT gate drivers
Photovoltaic (PV) inverters
Motor drives
Power supplies
GENERAL DESCRIPTION
The ADuM4136 is a single-channel gate driver specifically
optimized for driving insulated gate bipolar transistors (IGBTs).
Analog Devices, Inc., iCoupler® technology provides isolation
between the input signal and the output gate drive.
Operation with unipolar or bipolar secondary supplies is
possible, allowing negative gate drive if needed.
The Analog Devices chip scale transformers also provide isolated
communication of control information between the high voltage
and low voltage domains of the chip. Information on the status
of the chip can be read back from dedicated outputs. Control of
resetting the device after a fault on the secondary side is
performed on the primary side of the device.
Integrated onto the ADuM4136 is a desaturation detection
circuit that provides protection against high voltage short-
circuit IGBT operation. The desaturation protection contains
noise reducing features such as a 312 ns (typical) masking time
after a switching event to mask voltage spikes due to initial
turn-on. An internal 537 μA (typical) current source allows low
device count, and the internal blanking switch allows the
addition of an external current source if more noise immunity
is needed.
The secondary UVLO is set to 12 V with common IGBT
threshold levels taken into consideration.
FUNCTIONAL BLOCK DIAGRAM
VI+ 1
VI– 2
VDD1 3
VSS1 4
RESET 5
FAULT 6
1
1
READY 7
1
VSS1 8
1
1
ADuM4136
UVLO
MASTER
LOGIC
PRIMARY
ENCODE
DECODE
DECODE
ENCODE
MASTER
LOGIC
SECONDARY
UVLO
TSD
9V
2
16 GND2
15 VSS2
2
14 DESAT
13 VDD2
2 12 VDD2
11 VOUT
10 VSS2
2
2
9 VSS2
2
NOTES
1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE ISOLATED FROM EACH OTHER.
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADuM4136
Data Sheet
Parameter
Propagation Delay3
Propagation Delay Skew4
Output Rise/Fall Time (10% to 90%)
Blanking Capacitor Discharge Switch Masking
Time to Report Desaturation Fault to FAULT Pin
Common-Mode Transient Immunity (CMTI)
Static CMTI5
Dynamic CMTI6
Symbol
tDHL, tDLH
tPSK
tR/tF
tDESAT_DELAY
tREPORT
|CM|
Min
40
11
213
100
100
Typ Max
55 68
15
16 22.9
312 615
1.3 2
Unit
ns
ns
ns
ns
μs
Test Conditions/Comments
CL
=
2
nF,
VDD2
=
15
V,
RGON2
=
R2
GOFF
=
3.9
Ω
CL
=
2
nF,
RGON2
=
R2
GOFF
=
3.9
Ω
CL
=
2
nF,
VDD2
=
15
V,
RGON2
=
R2
GOFF
=
3.9
Ω
kV/μs VCM = 1500 V
kV/μs VCM = 1500 V
1 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
2 See the Power Dissipation section.
3 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUT signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOUT signal. See Figure 22 for waveforms of propagation delay parameters.
4 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 22 for waveforms of propagation delay parameters.
5 Static common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2 with inputs held either high or low such that the output voltage remains
either above 0.8 × VDD2 for output high, or 0.8 V for output low. Operation with transients above the recommended levels can cause momentary data upsets.
6 Dynamic common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test pulse.
Operation with transients above the recommended levels can cause momentary data upsets.
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input Side to High-Side Output)1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Junction to Ambient Thermal Resistance
Junction to Case Thermal Resistance
Symbol
RI-O
CI-O
CI
θJA
θJC
Min Typ Max Unit Test Conditions/Comments
1012 Ω
2.0 pF
4.0 pF
75.4 °C/W 4-layer printed circuit board (PCB)
35.4 °C/W 4-layer PCB
1 The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
REGULATORY INFORMATION
The ADuM4136 is pending approval by the organizations listed in Table 3.
Table 3.
UL (Pending)
Recognized under UL 1577
Component Recognition Program1
Single Protection,
5000 V rms Isolation Voltage
File E214100
CSA (Pending)
Approved under CSA Component Acceptance Notice 5A
Basic insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1
2nd Ed.+A1+A2, 780 V rms (1103 V peak) maximum working voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1 Second Ed.+A1+A2,
390 V rms (551 V peak) maximum working voltage
File 205078
VDE (Pending)
Certified according to VDE0884-102
Basic insulation, 849 V peak
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM4136 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM4136 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge
detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
7.8 min
Minimum External Tracking (Creepage)
L(I02) 7.8 min
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.026 min
>400
II
Unit
V rms
mm
mm
mm
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals, shortest
distance through air
Measured from input terminals to output terminals, shortest
distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. 0 | Page 4 of 16
5 Page 
ADuM4136
80
70
tDHL
60
tDLH
50
40
30
20
10
0
–40 –20
0 20 40 60 80
AMBIENT TEMPERATURE (°C)
100 120
Figure 16. Propagation Delay vs. Ambient Temperature,
VDD2 = 5 V, VDD2 − VSS2 = 12 V
CH1 = VI+ (5V/DIV)
1 CH2 = VGATE (10V/DIV)
2
CH3 = FAULT (5V/DIV)
3
4
CH4 = DESAT (5V/DIV)
CH1 5V CH2 10V
CH3 5V CH4 5V
500ns/DIV
A CH1 1.1V
2.5GS/s 400ps/PT
Figure 17. Example Desaturation Event and Reporting
800
700
SOURCE RESISTANCE
600
500
SINK RESISTANCE
400
300
200
100
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 18. Output On Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
Tested at 250 mA
Data Sheet
800
700
SOURCE RESISTANCE
600
500
SINK RESISTANCE
400
300
200
100
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 19. Output On Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
Tested at 1 A
CH1 = VI+ (5V/DIV)
1
2
CH2 = VGATE (5V/DIV)
CH3 = RESET (5V/DIV)
3
CH1 5V CH2 5V
CH3 5V
500ns/DIV
A CH3
2.5GS/s 400ps/PT
Figure 20. Example RESET to Output Valid
3.3V
10
9
8 PEAK SINK IOUT
7
6
PEAK SOURCE IOUT
5
4
3
2
1
0
12.0
14.5 17.0 19.5 22.0
OUTPUT SUPPLY VOLTAGE (V)
24.5
Figure 21. Peak Output Current vs. Output Supply Voltage,
2.4 Ω Series Resistance (IOUT is the Current Going Into/Out Of the Device Gate)
Rev. 0 | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADUM4136.PDF ] | |
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