PDF TMPM363F10FG Data sheet ( Hoja de datos )

Número de pieza	TMPM363F10FG
Descripción	32 Bit RISC Microcontroller
Fabricantes	Toshiba
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No Preview Available ! 32 Bit RISC Microcontroller TX03 Series TMPM363F10FG 1 page TMPM363F10FG 1.2.2 SAMCR(Control register) 31 30 29 28 27 bit symbol - - - - - After reset 0 0 0 0 0 23 22 21 20 19 bit symbol - - - - - After reset 0 0 0 0 0 15 14 13 12 11 bit symbol - - - - - After reset 0 0 0 0 0 76543 bit symbol MODE TDATA After reset 0 0 0 1 0 Bit 31-10 9-7 6-0 Bit Symbol − MODE[2:0] TDATA[6:0] Type R R/W W Function "0" can be read. Operation mode settings 000 : Sample mode 0 001 : Sample mode 1 010 : Sample mode 2 011 : Sample mode 3 The settings other than those above: Reserved Transmitted data Note: The Type is divided into three as shown below. 26 - 0 18 - 0 10 - 0 2 0 25 24 -- 00 17 16 -- 00 98 MODE 00 10 00 R/W R W READ WRITE READ WRITE c. Data descriptopn Meanings of symbols used in the SFR description are as shown below. ・ x:channel numbers/ports ・ n,m:bit numbers d. Register descriptoption Registers are described as shown below. ・ Register name <Bit Symbol> Exmaple: SAMCR<MODE>="000" or SAMCR<MODE[2:0]>="000" <MODE[2:0]> indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width). 5 Page 7.1.1 Exception types..................................................................................................................................................................63 7.1.2 Handling Flowchart...........................................................................................................................................................64 7.1.2.1 Exception Request and Detection 7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) 7.1.2.3 Executing an ISR 7.1.2.4 Exception exit 7.2 Reset Exceptions.....................................................................................................................70 7.3 Non-Maskable Interrupts (NMI).............................................................................................70 7.4 SysTick....................................................................................................................................70 7.5 Interrupts..................................................................................................................................71 7.5.1 Interrupt Sources................................................................................................................................................................71 7.5.1.1 Interrupt route 7.5.1.2 Generation 7.5.1.3 Transmission 7.5.1.4 Precautions when using external interrupt pins 7.5.1.5 List of Interrupt Sources 7.5.1.6 Active level 7.5.2 Interrupt Handling.............................................................................................................................................................77 7.5.2.1 Flowchart 7.5.2.2 Preparation 7.5.2.3 Detection by Clock Generator 7.5.2.4 Detection by CPU 7.5.2.5 CPU processing 7.5.2.6 Interrupt Service Routine (ISR) 7.6 Exception / Interrupt-Related Registers..................................................................................83 7.6.1 Register List.......................................................................................................................................................................83 7.6.2 NVIC Registers..................................................................................................................................................................84 7.6.2.1 SysTick Control and Status Register 7.6.2.2 SysTick Reload Value Register 7.6.2.3 SysTick Current Value Register 7.6.2.4 SysTick Calibration Value Register 7.6.2.5 Interrupt Set-Enable Register 1 7.6.2.6 Interrupt Set-Enable Register 2 7.6.2.7 Interrupt Set-Enable Register 3 7.6.2.8 Interrupt Set-Enable Register 4 7.6.2.9 Interrupt Clear-Enable Register 1 7.6.2.10 Interrupt Clear-Enable Register 2 7.6.2.11 Interrupt Clear-Enable Register 3 7.6.2.12 Interrupt Clear-Enable Register 4 7.6.2.13 Interrupt Set-Pending Register 1 7.6.2.14 Interrupt Set-Pending Register 2 7.6.2.15 Interrupt Set-Pending Register 3 7.6.2.16 Interrupt Set-Pending Register 4 7.6.2.17 Interrupt Clear-Pending Register 1 7.6.2.18 Interrupt Clear-Pending Register 2 7.6.2.19 Interrupt Clear-Pending Register 3 7.6.2.20 Interrupt Clear-Pending Register 4 7.6.2.21 Interrupt Priority Register 7.6.2.22 Vector Table Offset Register 7.6.2.23 Application Interrupt and Reset Control Register 7.6.2.24 System Handler Priority Register 7.6.2.25 System Handler Control and State Register 7.6.3 Clock generator registers.................................................................................................................................................110 7.6.3.1 CGIMCGA (CG Interrupt Mode Control Register A) 7.6.3.2 CGIMCGB (CG Interrupt Mode Control Register B) 7.6.3.3 CGIMCGE (CG Interrupt Mode Control Register E) 7.6.3.4 CGIMCGF (CG Interrupt Mode Control Register F) 7.6.3.5 CGICRCG (CG Interrupt Request Clear Register) 7.6.3.6 CGNMIFLG (NMI Flag Register) 7.6.3.7 CGRSTFLG (Reset Flag Register) 8. Input / Output Ports 8.1 Port Functions........................................................................................................................121 8.1.1 Function list.....................................................................................................................................................................121 8.1.2 Port Registers Outline.....................................................................................................................................................124 8.1.3 Port states in STOP Mode...............................................................................................................................................125 8.2 Port functions.........................................................................................................................126 8.2.1 Port A (PA0 to PA7).......................................................................................................................................................126 iii 11 Page

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