PDF MC74HCT08A Data sheet ( Hoja de datos )

Número de pieza	MC74HCT08A
Descripción	Quad 2-Input AND Gate
Fabricantes	ON Semiconductor
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No Preview Available ! MC74HCT08A Quad 2-Input AND Gate with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT08A is identical in pinout to the LS08. The device inputs are compatible with Standard CMOS or LSTTL outputs. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 V to 6.0 V • Low Input Current: 1 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance With the JEDEC Standard No. 7A Requirements • Chip Complexity: 24 FETs or 6 Equivalent Gates • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These are Pb−Free Devices A1 1 B1 2 3 Y1 A2 4 B2 5 A3 9 B3 10 6 Y2 Y = AB 8 Y3 A4 12 B4 13 11 Y4 PIN 14 = VCC PIN 7 = GND Figure 1. Logic Diagram Pinout: 14−Lead Packages (Top View) VCC B4 A4 Y4 B3 A3 Y3 14 13 12 11 10 9 8 14 1 http://onsemi.com MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 1 HCT08AG AWLYWW 14 14 TSSOP−14 DT SUFFIX 1 CASE 948G HCT 08 ALYW G G 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs Output AB Y LL LH HL HH L L L H ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. 1234567 A1 B1 Y1 A2 B2 Y2 GND Figure 2. Pinout © Semiconductor Components Industries, LLC, 2014 February, 2014 − Rev. 9 1 Publication Order Number: MC74HCT08A/D 1 page MC74HCT08A PACKAGE DIMENSIONS 0.15 (0.006) T U S 2X L/2 14 L PIN 1 IDENT. 1 14X K REF TSSOP−14 CASE 948G ISSUE B 0.10 (0.004) M T U S V S N 8 B −U− N 0.25 (0.010) M F 7 DETAIL E 0.15 (0.006) T U S A −V− K J J1 ÇÇÉÉÇÇÉÉK1ÇÇÉÉ SECTION N−N 0.10 (0.004) −T− SEATING PLANE D C G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. −W− MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 5 Page

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