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PDF STC15W201S Data sheet ( Hoja de datos )
| Número de pieza | STC15W201S | |
| Descripción | MCU | |
| Fabricantes | STC MCU | |
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*HQHUDO2YHUYLHZRI67&:6VHULHV0&8
General Overview of STC15W201S series MCU
1. Introduction of STC15W201S series MCU (In abundant supply)
STC15W201S series MCU is a single-chip microcontroller based on a high performance 1T architecture
8051 CPU, which is produced by STC MCU Limited. It is a new generation of 8051 MCU of high speed, high
stability, wide voltage range, low power consumption and super strong anti-disturbance. Besides, STC15W201S
series MCU is a MCU of super advanced encryption, because it adopts the ninth generation of STC encryption
technology. With the enhanced kernel, STC15W201S series MCU is faster than a traditional 8051 in executing
instructions (about 8~12 times the rate of a traditional 8051 MCU), and has a fully compatible instruction set
with traditional 8051 series microcontroller. External expensive crystal can be removed by being integrated
internal high-precise R/C clock(f0.3%) with f1% temperature drift (-40ć~+85ć) while f0.6% in normal
temperature (-20ć~+65ć) and wide frenquency adjustable between 5MHz and 35MHz. External reset curcuit
also can be removed by being integrated internal highly reliable one with 16 levels optional threshold voltage of
reset. The STC15W201S series MCU includes a high-speed asynchronous serial port----UART( can be regarded
as 2 serial ports by shifting among 2 groups of pins), comparator and so on. STC15W201S series MCU is usually
used in serial communication or electrical control or some occasion with strong disturbance.
In Keil C development environment, select the Intel 8052 to compiling and only contain < reg51.h > as head-
er file.
STC15 series MCU with super high-speed CPU core of STC-Y5 works 20% faster than STC early 1T series
(such as STC12/STC11/STC10 series) at same clock frequency.
• Enhanced 8051 Central Processing Unit, 1T, single clock per machine cycle, faster 8~12 times than the rate of
a traditional 8051.
• Operating voltage range: 5.5V ~ 2.4V.
• On-chip 1K/2K/3K/4K/5K/7.5K FLASH program memory with flexible ISP/IAP capability, can be repeatedly
erased more than 100 thousand times.
• on-chip 256 bytes SRAM
• On-chip EEPROM with large capacity can be repeatedly erased more than 100 thousand times.
• ISP/IAP, In-System-Programming and In-Application-Programming , no need for programmer and emulator.
• Internal hghly reliable Reset with 16 levels optional threshold voltage of reset, external reset curcuit can be
completely removed
• Internal high- precise R/C clock(f0.3%) with f1% temperature drift (-40ć~+85ć) while f0.6% (-20ć
~+65ć) in normal temperature and wide frenquency adjustable between 5MHz and 35MHz (5.5296MHz /
11.0592MHz / 22.1184MHz / 33.1776MHz).
• Operating frequency range: 0- 35MHz, is equivalent to traditional 8051:0~420MHz.
• No need external crystal and reset, and can output clock and low reset signal from MCU.
• A high-speed asynchronous serial ports----UART ( can be regarded as 2 serial ports by shifting among 2
groups of pins): UART1(RxD/P3.0, TxD/P3.1) can be switched to (RxD_2/P3.6, TxD_2/P3.7).
• Support the function of Encryption Download (to protect your code from being intercepted).
• Support the function of RS485 Control
• Code protection for flash memory access, excellent noise immunity, very low power consumption
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Mnemonic Add Name 7 6 5 4 3 2 1 0 Reset Value
CLK_DIV
(PCON2)
97H
Clock Division
register
MCKO_S1 MCKO_S0
ADRJ
Tx_Rx Tx2_Rx2 CLKS2 CLKS1 CLKS0
00x0,x000
MCKO_S1
0
0
1
1
MCKO_S0
the control bit of master clock output by dividing the frequency
(The master clock can either be internal R/C clock or the external input clock or the external crystal oscillator)
0 Master clock do not output external clock
1
Master clock output external clockˈbut its frequency do not be dividedˈand the output clock
frequency = MCLK / 1
0
Master clock output external clockˈbut its frequency is divided by 2ˈand the output clock
frequency = MCLK / 2
1
Master clock output external clockˈbut its frequency is divided by 4ˈand the output clock
frequency = MCLK / 4
The master clock can either be internal R/C clock or the external input clock or the external crystal oscillator.
MCLK is the frequency of master clock.
STC15204SW series MCU output master clock on MCLKO/P5.4
Limited.It is on MCLKO/P3.4 that the Programmable clock output of master clock of STC15 series 8-pin MCU (such as STC15F101W
series). However, it is on MCLKO/P5.4 that the Programmable clock output of master clock of other STC15 series MCU
including 16-pin or more than 16-pin MCU.
Tx_Rx˖the set bit of relay and broadcast mode of UART1
0˖UART1 works on normal mode
CU1˖UART1 works on relay and broadcast modeˈthat to say output the input level state of RxD port to the
outside TxD pin in real time, namely the external output of TxD pin can reflect the input level state of RxD
Mport.
the RxD and TxD of UART1 can be switched in 3 groups of pins: [RxD/P3.0, TxD/P3.1];
STC [RxD_2/P3.6, TxD_2/P3.7];
[RxD_3/P1.6, TxD_3/P1.7].
CLKS2
CLKS1
CLKS0
the control bit of system clock
(System clock refers to the master clock that has been divided frequency, which is offered to CPU and Timers)
0 0 0 Master clock frequency/1, No division
0 0 1 Master clock frequency/2
0 1 0 Master clock frequency/4
0 1 1 Master clock frequency/8
1 0 0 Master clock frequency/16
1 0 1 Master clock frequency/32
1 1 0 Master clock frequency/64
1 1 1 Master clock frequency/128
The master clock can either be internal R/C clock or the external input clock or the external crystal oscillator.
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7. Pin Descriptions of STC15W201S series MCU
Pin Number
MNEMONIC
SOP16/
SOP8
DIP16
DESCRIPTION
P1.0/
RSTOUT_LOW
P1.0 common I/O port PORT1[0]
15
RSTOUT_LOW
the pin output low after power-on
output high by software
and
during
reset,
which
can
be
set
to
P1.1 16 common I/O port PORT1[1]
P1.2 common I/O port PORT1[2]
P1.2/T0/CMPO
1 T0 External input of Timer/Counter 0
CMPO The output port of reslut compared by comparator
P1.3 2 common I/O port PORT1[3]
P1.4 common I/O port PORT1[5]
P1.4/T0CLKO
3 T0 Clock Output
T0CLKO The pin can be configured for T0CLKO by setting INT_CLKO[0] bit
/T0CLKO
P1.5 4 common I/O port PORT1[5]
P3.0 common I/O port PORT3[0]
RxD Receive Data Port of UART
P3.0/RxD/INT4 5
/T2CLKO
9
INT4
T2CLKO
External interrupt 4, which only can be generated on falling edge.
INT4 supports power-down waking-up
T2 Clock Output
The pin can be configured for T2CLKO by setting INT_CLKO[2] bit
/T2CLKO
P3.1 common I/O port PORT3[1]
P3.1/TxD/T2 6 10
TxD Transit Data Port of UART
T2 External input of Timer/Counter 2
P3.2 common I/O port PORT3[2]
P3.2/INT0
7 11
INT0
External interrupt 0, which both can be generated on rising and falling edge.
INT0 only can generate interrupt on falling edge if IT0 (TCON.0) is set to
1. And, INT0 both can generate interrupt on rising and falling edge if IT0
(TCON.0) is set to 0.
P3.3 common I/O port PORT3[3]
P3.3/INT1
8 12
INT1
External interrupt 1, which both can be generated on rising and falling edge.
INT1 only can generate interrupt on falling edge if IT1 (TCON.2) is set to
1. And, INT1 both can generate interrupt on rising and falling edge if IT1
(TCON.2) is set to 0.
INT1 supports power-down waking-up
P3.6 common I/O port PORT3[6]
P3.6/INT2/RxD_2
External interrupt 2, which only can be generated on falling edge.
13
INT2
INT2 supports power-down waking-up
RxD_2 Receive Data Port of UART
P3.7 common I/O port PORT3[7]
P3.7/INT3/TxD_2
External interrupt 3, which only can be generated on falling edge.
14
INT3
INT3 supports power-down waking-up
TxD_2 Transit Data Port of UART
11 Page | ||
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| PDF Descargar | [ Datasheet STC15W201S.PDF ] | |
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